K4S643234E-TE/N
CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL
Extended Low Power (2.5V)
Revision 1.0
January 2001
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.0 (Jan. 2001)
K4S643234E-TE/N
Revision History
Revision 1.0 (January 12, 2000)
• Final spec
CMOS SDRAM
Revision 0.0 (December 20, 2000) -
Preliminary Spec.
• Initial draft
-2-
Rev. 1.0 (Jan. 2001)
K4S643234E-TE/N
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
•
•
•
•
2.5V±5% power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle(4K/64ms)
Extended temperature range : (-25°C to +85°C)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S643234E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
•
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4S643234E-TE/N60
K4S643234E-TE/N70
Max Freq.
166MHz
143MHz
Interface
LVTTL
Package
86
TSOP(II)
• -E/N : Extended temperature (-25°C to +85°C)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
-3-
Rev. 1.0 (Jan. 2001)
K4S643234E-TE/N
PIN CONFIGURATION
(Top view)
CMOS SDRAM
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
N.C
V
DD
DQM0
WE
CAS
RAS
CS
N.C
BA0
BA1
A10/AP
A0
A1
A2
DQM2
V
DD
N.C
DQ16
V
SSQ
DQ17
DQ18
V
DDQ
DQ19
DQ20
V
SSQ
DQ21
DQ22
V
DDQ
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
N.C
V
SS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
N.C
DQ31
V
DDQ
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DDQ
DQ26
DQ25
V
SSQ
DQ24
V
SS
86Pin TSOP (II)
(400mil x 875mil)
(0.5 mm Pin pitch)
-4-
Rev. 1.0 (Jan. 2001)
K4S643234E-TE/N
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
CMOS SDRAM
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
CKE
Clock enable
A
0
~ A
10
BA0,1
RAS
CAS
WE
DQM0 ~ 3
DQ
0
~
31
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No Connection
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
-5-
Rev. 1.0 (Jan. 2001)
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