ZL30343
SyncE/SONET/SDH G.8262/Stratum3 SETS
& IEEE 1588 Packet G.8261 Synchronizer
Short-Form Data Sheet
Features
•
Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.813, and G.781
SETS
Supports ITU-T G.823, G.824 and G.8261 for
2048 kbit/s and 1544 kbit/s interfaces
Frequency, Phase and Time Synchronization over
IP, MPLS and Ethernet Packet Networks
•
Frequency accuracy performance for WCDMA-
FDD, GSM, LTE-FDD and femtocell
applications, with target performance less than
± 15 ppb.
Frequency performance for ITU-T G.823 and
G.824 synchronization interface, as well as
G.8261 PNT EEC, PNT PEC and CES interface
specifications.
Phase Synchronization performance for
WCDMA-TDD, Mobile WiMAX, TD-SCDMA and
CDMA2000 applications with target
performance less than ± 1
s
phase alignment.
Time Synchronization for UTC-traceability and
GPS replacement.
•
•
June 2012
Ordering Information
ZL30343GGG
100 Pin CABGA
Trays
ZL30343GGG2 100 Pin CABGA*
Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz
Generates standard SONET/SDH clock rates
(e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, 622.08 MHz) or Ethernet clock rates
(e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz,
312.5 MHz) for synchronizing Gigabit Ethernet
PHYs
Provides two DPLLs which are independently
configurable through a serial interface
Client reference switching between multiple
Servers
Client holdover when Server packet connectivity is
lost
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•
dpll2_ref
osci
osco
ref
m
DPLL2
T4
P1
Synthesizer
p1_clk0
p1_clk1
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
ref8
sync0
sync1
sync2
sync8
Software
PLL Control
(over I2C/SPI)
/N1
/N2
P0
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
diff0
Input
Ports
ref
n
/sync
n
DPLL1
T0
SONET/SDH/
Ethernet
APLL
diff1
apll_clk0
apll_clk1
apll_fp0
apll_fp1
fb_clk
ext_fb_clk
ext_fb_fp
Ref/Sync
Monitors
Feedback
Synthesizer
mode
lock
hold
I
2
C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2012, Microsemi Corporation. All Rights Reserved.
ZL30343
1.0
1.1
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•
Short-Form Data Sheet
Features
Time Synchronization Algorithm
External algorithm controls software digital PLL to adjust frequency & phase alignment
Frequency, Phase and Time Synchronization over IP, MPLS and Ethernet Packet Networks
Frequency accuracy performance for WCDMA-FDD, GSM, LTE-FDD and femtocell applications, with target
performance less than ± 15 ppb.
Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC,
PNT PEC and CES interface specifications.
Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA and CDMA2000
applications with target performance less than ± 1
s
phase alignment.
Time Synchronization for UTC-traceability and GPS replacement.
Client reference switching between multiple Servers
Client holdover when Server packet connectivity is lost
1.2
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Electrical Clock Engine
Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1
and 2)
Supports the requirements of Telcordia GR-1244 Stratum 3 and GR-253, ITU-T G.813, and G.781 SETS
Supports ITU-T G.823, G.824 and G.8261 for 2048 kbit/s and 1544 kbit/s interfaces
Meets the SONET/SDH jitter generation requirements up to OC-48/STM-16
Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet
reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz)
Supports composite clock inputs (64 kHz, 64 kHz + 8 kHz, 64 kHz + 8 kHz + 400 Hz)
Provides two DPLLs which are independently configurable through a serial interface
Internal state machine automatically controls mode of operation (free-run, locked, holdover)
Flexible input reference monitoring automatically disqualifies references based on frequency and phase
irregularities
Supports master/slave configuration and dynamic input to output delay compensation for AdvancedTCA
TM
Provides automatic reference switching and holdover during loss of reference input
1.3
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Electrical Clock Generation
Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any multiple of 8 kHz
up to 100 MHz
Generates several styles of telecom frame pulses with selectable pulse width, polarity and frequency
Configurable input to output delay and output to output phase alignment
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2
Microsemi Corporation
ZL30343
1.4
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Short-Form Data Sheet
API Software
Interfaces to 1588-capable PHY and switches with integrated timestamping
Abstraction layer for independence from OS and CPU, from embedded SoC to home-grown
Fits into centralized, highly integrated pizza box architectures as well as distributed architectures with
multiple line cards and timing cards
2.0
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Applications
ITU-T G.8262 System Timing Cards which support 1 GbE and 10 GbE interfaces
Telcordia GR-253 Carrier Grade SONET/SDH Stratum 3 System Timing Cards
System Timing Cards which supports ITU-T G.781 SETS (SDH Equipment Timing Source)
Integrated basestation reference clock for air interface for GSM, WCDMA, LTE and WiMAX macro, micro or
femtocells
Mobile Backhaul NID, edge router or access aggregation node
EPON/GE-PON & GPON OLT
EPON/GE-PON & GPON ONU/OLT
DSLAM and RT-DSLAM
3
Microsemi Corporation
ZL30343
Short-Form Data Sheet
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
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