KLI-2113
Linear CCD Image Sensor
Description
The KLI−2113 Image Sensor is a high dynamic range, multispectral,
linear CCD image sensor ideally suited for demanding color scanner
applications.
The imager consists of three parallel 2098-element photodiode
arrays − one for each primary color. The KLI−2113 sensor offers high
sensitivity, a high data rate, low noise, and negligible lag. Independent
exposure control for each channel allows color balancing at the front
end. CMOS-compatible 5 V clocks, and single 12 V DC supply are all
that are required to drive the KLI−2113 sensor, simplifying the design
of interface electronics.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Pixels Count
Pixel Size
Pixel Pitch
Inter-Array Spacing
Active Image Size
Saturation Signal
Dynamic Range
Responsivity (Wavelength)
R, G, B (−RAA)
R, G, B (−DAA)*
Mono (−AAA, −AAB)
Output Sensitivity
Dark Current
Dark Current Doubling Rate
Charge Transfer Efficiency
Photoresponse Non-Uniformity
Lag (First Field)
Maximum Data Rate
Package
Cover Glass
Typical Value
3 Channel, RGB Tri-linear CCD
2098
×
3
14
mm
(H)
×
14
mm
(V)
14
mm
112 mm (8 Lines Effective)
29.37 mm (H)
×
0.24 mm (V)
29.4 mm (Diagonal)
170,000 e
−
76 dB
62, 42, 37 V/mJ/cm
2
60, 40, 36 V/mJ/cm
2
66 V/mJ/cm
2
11.5
mV/e
−
0.02 pA/Pixel
9°C
0.99999/Transfer
5% Peak-Peak
0.6%
20 MHz/Channel
CERDIP (Sidebrazed, CuW)
AR Coated, 2 Sides
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Figure 1. KLI−2113 Linear CCD
Image Sensor
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Resolution
Wide Dynamic Range
High Sensitivity
High Operating Speed
High Charge Transfer Efficiency
No Image Lag
Electronic Exposure Control
Pixel Summing Capability
Up to 2.0 V Peak-Peak Output
5.0 V Clock Inputs
Two-Phase Register Clocking
On-Chip Dark Reference
Applications
*
Configuration KLI-2113-DAA uses Gen1 color filter set and is not recommended
for new designs.
NOTE: Parameters above are specified at T = 25°C and 2 MHz clock rates unless
otherwise noted.
Digitization
Machine Vision
Mapping/Aerial
Photography
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
November, 2015 − Rev. 5
Publication Order Number:
KLI−2113/D
KLI−2113
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KLI−2113 IMAGE SENSOR
Part Number
KLI−2113−AAA−ER−AA
KLI−2113−AAA−ER−AE
KLI−2113−AAB−ED−AA
KLI−2113−AAB−ED−AE
KLI−2113−RAA−ED−AA
KLI−2113−RAA−ED−AE
KLI−2113−DAA−ED−AA*
KLI−2113−DAA−ED−AE*
Description
Monochrome, No Microlens, CERDIP Package (Leadframe),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
Monochrome, No Microlens, CERDIP Package (Leadframe),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
Monochrome, No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Monochrome, No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KLI−2113 Lot Number
Serial Number
KLI−2113 Lot Number
Serial Number
KLI−2113 Lot Number
Serial Number
Marking Code
KLI−2113 Lot Number
Serial Number
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KLI−2113−12−5−A−EVK
Evaluation Board (Complete Kit)
Description
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KLI−2113
DEVICE DESCRIPTION
LS
LOGn
Photodiode Array
IG
ID
f2
f1
f2s
SUB
SUB
TG1
TG2
2 Blank
CCD Cells
4 Blank
CCD Cells
VIDn
FD
12 Test
2098 Active Pixels
12 Dark
f
R
RD
VDD
Figure 2. Single Channel Schematic
Exposure Control
Exposure control is implemented by selectively clocking
the LOG gates during portions of the scanning line time. By
applying a large enough positive bias to the LOG gate,
the channel potential is increased to a level beyond the
‘pinning level’ of the photodiode. (The ‘pinning’ level is the
maximum channel potential that the photodiode can achieve
and is fixed by the doping levels of the structure.) With TG1
in an ‘off’ state and LOG strongly biased, all of the
photocurrent will be drawn off to the LS drain. Referring to
Figure 9, one notes that the exposure can be controlled by
pulsing the LOG gate to a ‘high’ level while TG1 is turning
‘off’ and then returning the LOG gate to a ‘low’ bias level
sometime during the line scan. The effective exposure (t
EXP
)
is the net time between the falling edge of the LOG gate and
the falling edge of the TG1 gate (end of the line). Separate
LOG connections for each channel are provided, enabling
on-chip light source and image spectral color balancing. As
a cautionary note, the switching transients of the LOG gates
during line readout may inject an artifact at the sensor
output. Rising edge artifacts can be avoided by switching
LOG during the photodiode-to-CCD transfer period,
preferably, during the TG1 falling edge. Depending on
clocking speeds, the falling edge of the LOG should be
synchronous with the
f1/f2
shift register readout clocks.
For very fast applications, the falling edge of the LOG gate
may be limited by on-chip RC delays across the array. In this
case, artifacts may extend across one or more pixels.
Correlated double sampling (CDS) processing of the output
waveform can remove the first order magnitude of such
artifacts. In high dynamic range applications, it may be
advisable to limit the LOG fall times to minimize the current
transients in the device substrate and limit the magnitude of
the artifact to an acceptable level.
Pixel Summing
The effective resolution of this sensor can be varied by
enabling the pixel summing feature. A separate pin is
provided for the last shift register gate labeled
f2s.
This
gate, when clocked appropriately, stores the summation of
signal from adjacent pixels. This combined charge packet is
then transferred onto the sense node. As an example,
the sensor can be operated in 2-pixel summing mode
(1,049 pixels), by supplying a
f2s
clock which is a 75% duty
cycle signal at 1/2 the frequency of the
f2
signal, and
modifying the
fR
clock as depicted in Figure 10.
Applications that require full resolution mode
(2,098 pixels), must tie the
f2s
pin to the
f2
pin. Refer to
Figure 9 and Figure 10 for additional details.
Image Acquisition
During the integration period, an image is obtained by
gathering electrons generated by photons incident upon the
photodiodes. The charge collected in the photodiode array
is a linear function of the local exposure. The charge is stored
in the photodiode itself and is isolated from the CCD shift
registers during the integration period by the transfer gates
TG1 and TG2, which are held at barrier potentials. At the
end of the integration period, the CCD register clocking is
stopped with the
f1
and
f2
gates being held in a ‘high’ and
‘low’ state respectively. Next, the TG gates are turned ‘on’
causing the charge to drain from the photo-diode into the
TG1 storage region. As TG1 is turned back ‘off’, charge is
transferred through TG2 and into the
f1
storage region.
The TG2 gate is then turned ‘off’, isolating the shift registers
from the accumulation region once again. Complementary
clocking of the
f1
and
f2
phases now resumes for readout
of the current line of data while the next line of data is
integrated.
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3
KLI−2113
Charge Transport
Readout of the signal charge is accomplished by
two-phase, complementary clocking of the Phase 1 and
Phase 2 gates (f1 and
f2)
in the horizontal (output) shift
register. The register architecture has been designed for high
speed clocking with minimal transport and output signal
degradation, while still maintaining low (4.75 V
P−P
min)
clock swings for reduced power dissipation, lower clock
noise and simpler driver design. The data in all registers is
clocked simultaneously toward the output structures.
The signal is then transferred to the output structures in
a parallel format at the falling edge of the
f2s
clock.
Resettable floating diffusions are used for the charge to
voltage conversion while source followers provide
buffering to external connections. The potential change on
the floating diffusion is dependent on the amount of signal
charge and is given by
DV
FD
=
DQ
/ C
FD
, where
DV
FD
is the
change in potential on the floating diffusion,
DQ
is the
amount of charge, and C
FD
is the capacitance of the floating
diffusion node. Prior to each pixel output, the floating
diffusion is returned to the RD level by the reset clock,
fR.
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KLI−2113
Physical Description
Pin Description and Device Orientation
VIDR
SUB
RD
fR
LOGR
LOGG
SUB
1
2
3
4
5
6
7
28
27
26
25
24
23
22
VIDG
SUB
VDD
VIDB
SUB
N/C
LOGB
N/C
LS
IG
TG2
N/C
f2s
f2
8
9
10
11
12
13
14
21
20
19
18
17
16
15
N/C
N/C
ID
TG1
N/C
N/C
f1
Figure 3. KLI−2113 Pinout
Table 4. PACKAGE PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
VIDR
SUB
RD
fR
LOGR
LOGG
SUB
N/C
LS
IG
TG2
N/C
f2s
f2
Description
Red Output Video
Substrate
Reset Drain
Reset Clock
Red Overflow Gate
Green Overflow Gate
Substrate
No Connection
Light Shield/Exposure Drain
Input Gate/LOG Test Pin
Outer Transfer Gate
No Connection
Phase2 Shift Register Summing Gate Clock
Phase2 Shift Register Clock
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
f1
N/C
N/C
TG1
ID
N/C
N/C
LOGB
N/C
SUB
VIDB
VDD
SUB
VIDG
Description
Phase1 Shift Register Clock
No Connection
No Connection
Inner Transfer Gate
Input Diode Test Pin
No Connection
No Connection
Blue Overflow Gate
No Connection
Substrate
Blue Output Video
Amplifier Supply
Substrate
Green Output Video
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