IDTCV123PV8 datasheet, PDF - EEWORLD Datasheet

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IDTCV123PV8: DescriptionIC flexpc clk progr P4 56-ssop; Categorysemiconductor Analog mixed-signal IC; File Size87KB，16 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDTCV123PV8 Overview

IC flexpc clk progr P4 56-ssop

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IDTCV123

PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC™

CLOCK FOR P4 PROCESSOR

IDTCV123

FEATURES:

• One high precision PLL for CPU, with SSC and N program-

mable

• One high precision PLL for SRC/PCI/SATA, SSC and N pro-

grammable

• One high precision PLL for 96MHz/48MHz

• Band-gap circuit for differential outputs

• Supports spread spectrum modulation, down spread 0.5%

• Supports SMBus block read/write, index read/write

• Selectable output strength for REF

• Allows for CPU frequency to change to a higher frequency for

maximum system computing power

• Available in SSOP package

DESCRIPTION:

IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to

support up to 400MHz processor. This chip has three PLLs inside for CPU/

SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial

ATA clock provides high accuracy frequency. This device also implements

Band-gap referenced I

REF

to reduce the impact of V

variation on differential

outputs, which can provide more robust system performance.

Static PLL frequency divide error can be as low as 36 ppm, worse case 114

ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock

has its own Spread Spectrum selection, which allows for isolated changes

instead of affecting other clock groups.

OUTPUTS:

• 2*0.7V current –mode differential CPU CLK pair

• 8*0.7V current –mode differential SRC CLK pair, one dedicated

for SATA

• One CPU_ITP/SRC selectable CLK pair

• 8*PCI, 3 free running, 33.3MHz

• 1*96MHz, 1*48MHz

• 2*REF

KEY SPECIFICATION:

•

CPU/SRC CLK cycle to cycle jitter < 85ps

SATA CLK cycle to cycle jitter < 85ps

PCI CLK cycle to cycle jitter < 250ps

Static PLL frequency divide error < 114 ppm

Static PLL frequency divide error for 48MHz < 5 ppm

FUNCTIONAL BLOCK DIAGRAM

PLL1

SSC

N Programmable

CPU CLK

Output Buffers

Stop Logic

CPU[1:0]

XTAL

Osc Amp

CPU_ITP/SRC6

REF

REF[0:1]

ITP_EN

SDATA

SCLK

SM Bus

Controller

PLL2

SSC

N Programmable

SRC CLK

Output Buffer

Stop Logic

SRC[6:0]

SATA_SRC

PCI[5:0], PCIF[2:0]

REF

TT_PWRGD

#/PD

Control

Logic

FSA.B.C

PLL3

48MHz/96MHz

Output BUffer

DOT96

48MHz

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 2004

DSC-6538/6

IDTCV123PV8 Related Products

	IDTCV123PV8	IDTCV123PVG	IDTCV123PVG8
Description	IC flexpc clk progr P4 56-ssop	IC flexpc clk progr P4 56-ssop	IC flexpc clk progr P4 56-ssop

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