countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS100 (v5.0) February 6, 2009
www.xilinx.com
Product Specification
1
Virtex-5 Family Overview
R
Table 1:
Virtex-5 FPGA Family Members
Configurable Logic Blocks (CLBs)
Device
Block RAM Blocks
Max
(Kb)
DSP48E
Max
Array
Virtex-5
Slices
(2)
Distributed
18 Kb
(3)
36 Kb
(Row x Col) Slices
(1)
RAM (Kb)
Max RocketIO
Endpoint
Transceivers
(6)
PowerPC
Total
Max
Blocks for Ethernet
CMTs
(4)
Processor
I/O
User
(5)
PCI
MACs
Blocks
Banks
(8)
I/O
(7)
Express
GTP
GTX
XC5VLX30
XC5VLX50
XC5VLX85
XC5VLX110
XC5VLX155
XC5VLX220
XC5VLX330
XC5VLX20T
XC5VLX30T
XC5VLX50T
XC5VLX85T
XC5VLX110T
XC5VLX155T
80 x 30
120 x 30
120 x 54
160 x 54
160 x 76
4,800
7,200
12,960
17,280
24,320
320
480
840
1,120
1,640
2,280
3,420
210
320
480
840
1,120
1,640
2,280
3,420
520
780
1,520
4,200
1,500
2,400
380
820
1,240
1,580
2,280
32
48
48
64
128
128
192
24
32
48
48
64
128
128
192
192
288
640
1,056
80
96
64
128
256
320
384
64
96
192
256
384
384
576
52
72
120
216
296
424
424
648
168
264
488
1,032
456
648
136
296
456
596
912
32
48
96
128
192
192
1,152
1,728
3,456
4,608
6,912
6,912
2
6
6
6
6
6
6
1
2
6
6
6
6
6
6
2
6
6
6
6
6
2
6
6
6
6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
2
2
2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
8
12
12
16
16
16
24
8
12
16
24
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
40
48
8
16
16
20
24
13
17
17
23
23
23
33
7
12
15
15
20
20
20
27
12
15
19
27
20
20
12
19
20
24
27
400
560
560
800
800
800
1,200
172
360
480
480
680
680
680
960
360
480
640
960
680
680
360
640
680
840
960
160 x 108 34,560
240 x 108 51,840
60 x 26
80 x 30
120 x 30
120 x 54
160 x 54
160 x 76
3,120
4,800
7,200
12,960
17,280
24,320
288 10,368
26
36
60
108
148
212
212
936
1,296
2,160
3,888
5,328
7,632
7,632
XC5VLX220T 160 x 108 34,560
XC5VLX330T 240 x 108 51,840
XC5VSX35T
XC5VSX50T
XC5VSX95T
XC5VSX240T
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
80 x 34
120 x 34
160 x 46
240 x 78
200 x 58
240 x 78
80 x 38
160 x 38
160 x 56
200 x 56
240 x 68
5,440
8,160
14,720
37,440
23,200
37,440
5,120
11,200
16,000
20,480
30,720
324 11,664
84
132
244
3,024
4,752
8,784
516 18,576
228
8,208
324 11,664
68
148
228
2,448
5,328
8,208
298 10,728
456 16,416
Notes:
1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously
it was two LUTs and two flip-flops.)
2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks.
4. Each Clock Management Tile (CMT) contains two DCMs and one PLL.
5. This table lists separate Ethernet MACs per device.
6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150 Mb/s to
6.5 Gb/s.
7. This number does not include RocketIO transceivers.
8. Includes configuration Bank 0.
2
www.xilinx.com
DS100 (v5.0) February 6, 2009
Product Specification
R
Virtex-5 Family Overview
Virtex-5 FPGA Logic
•
•
•
On average, one to two speed grade improvement over
Virtex-4 devices
Cascadable 32-bit variable shift registers or 64-bit
distributed memory capability
Superior routing architecture with enhanced diagonal
routing supports block-to-block connectivity with
minimal hops
Up to 330,000 logic cells including:
−
−
−
−
Up to 207,360 internal fabric flip-flops with clock enable
(XC5VLX330)
Up to 207,360 real 6-input look-up tables (LUTs) with
greater than 13 million total LUT bits
Two outputs for dual 5-LUT mode gives enhanced
utilization
Logic expanding multiplexers and I/O registers
550 MHz Integrated Block Memory
•
•
•
•
Up to 16.4 Mbits of integrated block memory
36-Kbit blocks with optional dual 18-Kbit mode
True dual-port RAM cells
Independent port width selection (x1 to x72)
−
−
−
−
Up to x36 total per port for true dual port operation
Up to x72 total per port for simple dual port operation
(one Read port and one Write port)
Memory bits plus parity/sideband memory support for
x9, x18, x36, and x72 widths
Configurations from 32K x 1 to 512 x 72
(8K x 4 to 512 x 72 for FIFO operation)
Full and Empty flag with fully programmable Almost Full
and Almost Empty flags
•
•
Multirate FIFO support logic
−
550 MHz Clock Technology
•
Up to six Clock Management Tiles (CMTs)
−
−
−
−
−
−
−
−
−
−
Each CMT contains two DCMs and one PLL—up to
eighteen total clock generators
Flexible DCM-to-PLL or PLL-to-DCM cascade
Precision clock deskew and phase shift
Flexible frequency synthesis
Multiple operating modes to ease performance trade-off
decisions
Improved maximum input/output frequency
Fine-grained phase shifting resolution
Input jitter filtering
Low-power operation
Wide phase shift range
•
•
•
•
•
•
Synchronous FIFO support without Flag uncertainty
Optional pipeline stages for higher performance
Byte-write capability
Dedicated cascade routing to form 64K x 1 memory
without using FPGA routing
Integrated optional ECC for high-reliability memory
requirements
Special reduced-power design for 18 Kbit (and below)
operation
550 MHz DSP48E Slices
•
•
•
25 x 18 two’s complement multiplication
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation with optional accumulator cascade
to 96-bits
Integrated adder for complex-multiply or multiply-add
operation
Optional bitwise logical operation modes
Independent C registers per slice
Fully cascadable in a DSP column without external
routing resources
•
•
•
Differential clock tree structure for optimized low-jitter
clocking and precise duty cycle
32 global clock networks
Regional, I/O, and local clocks in addition to global
clocks
•
•
•
•
SelectIO Technology
•
•
•
Up to 1,200 user I/Os
Wide selection of I/O standards from 1.2V to 3.3V
Extremely high-performance
−
−
Up to 800 Mb/s HSTL and SSTL
(on all single-ended I/Os)
Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
ChipSync Source-Synchronous
Interfacing Logic
•
•
•
•
•
Works in conjunction with SelectIO technology to
simplify source-synchronous interfaces
Per-bit deskew capability built into all I/O blocks
(variable delay line on all inputs and outputs)
Dedicated I/O and regional clocking resources (pins
and trees)
Built-in data serializer/deserializer logic with
corresponding clock divider support in all I/O
Networking/telecommunication interfaces up to
1.25 Gb/s per I/O
•
•
•
True differential termination on-chip
Same edge capture at input and output I/Os
Extensive memory interface support
DS100 (v5.0) February 6, 2009
Product Specification
www.xilinx.com
3
Virtex-5 Family Overview
R
Digitally Controlled Impedance (DCI)
Active I/O Termination
•
•
•
Optional series or parallel termination
Temperature and voltage compensation
Makes board layout much easier
−
−
Reduces resistors
Places termination in the ideal location, at the signal
source or destination
System Monitor
•
•
•
On-Chip temperature measurement (±4°C)
On-Chip power supply measurement (±1%)
Easy to use, self-contained
−
−
−
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip
sensors
Automatic calibration of offset and gain error
DNL = ±0.9 LSBs maximum
0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs
Configuration
•
•
•
•
•
•
•
Support for platform Flash, standard SPI Flash, or
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