PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844002I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
F
EATURES
• Two LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS844002I is a 2 output LVDS Synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™
clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and
53.125MHz. The ICS844002I uses ICS’ 3
rd
generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS844002I is packaged in a small 20-pin
TSSOP package.
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
Input
Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
23.4375
F_SEL1 F_SEL0
0
0
1
1
0
0
1
0
1
0
M Divider
Value
24
24
24
24
24
N Divider
Value
3
4
6
12
3
M/N Divider
Value
8
6
4
2
8
Output
Frequency
(MHz)
212.5
159.375
106.25
53.125
187.5
P
IN
A
SSIGNMENT
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
nQ1
GND
V
DD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
ICS844002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
REF_CLK
Pulldown
26.5625MHz
2
Q0
1
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
nQ0
Q1
nQ1
0
M = 24 (fixed)
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844002I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 20
3, 4
5
Name
nc
V
DDO
Q0, nQ0
MR
Type
Unused
Power
Ouput
Input
Description
No connect.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pins.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
nPLL_SEL
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
REF_CLK
nXTAL_SEL
GND
nQ1, Q1
Input
Power
Input
Power
Input
Input
Input
Power
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
844002AGI
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 16, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844002I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
TBD
TBD
TBD
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
TBD
TBD
TBD
Maximum
2.625
2.625
2.625
Units
V
V
V
mA
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%
OR
2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465
or 2.5V
V
DD
= 3.465V or 2.5V,
V
IN
= 0V
-150
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
µA
844002AGI
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 16, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844002I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
40
1.45
50
Maximum
Units
mV
mV
V
mV
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
40
1.2
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
26.5625
Maximum
28.33
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
844002AGI
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 16, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844002I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum
186.67
140
93.33
46.67
TBD
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
0.65
0.61
0.74
0.64
0.80
400
Typical
Maximum
226.66
170
113.33
56.66
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
Parameter
f
OUT
Output Frequency
t
sk(o)
Output Skew; NOTE 1, 2
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
t
sk(o)
Output Skew; NOTE 2, 4
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
Minimum
186.67
140
93.33
46.67
TBD
0.65
0.61
0.74
0.64
0.80
430
Typical
Maximum
226.66
170
113.33
56.66
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844002AGI
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 16, 2006
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
