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M2004-01-625.0000

Description
IC pll freq translator 36clcc
Categorysemiconductor    Analog mixed-signal IC   
File Size309KB,10 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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M2004-01-625.0000 Overview

IC pll freq translator 36clcc

Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2004-01/-11
F
REQUENCY
T
RANSLATION
PLL
G
ENERAL
D
ESCRIPTION
The M2004 variants -01 and -11 are VCSO (Voltage
Controlled SAW Oscillator) based
clock generator PLLs designed for
clock frequency translation and jitter
attenuation in a high-speed data
communications system. The clock
multiplication ratio and output
divider ratio are pin selectable and
also configurable through serial programming. External
loop components allow the tailoring of PLL loop
response. The M2004-11 adds Hitless Switching with
Phase Build-out (HS/PBO) to ensure that reference
clock reselection does not disrupt the output clock.
Also read about device variants -21, -31, -41, and
-51 in the M2004-x1 Preliminary Information sheet.
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
M0
GND
REF_SEL
REF_CLK0
REF_CLK1
nP_LOAD
S_LOAD
S_DATA
VCC
M1
M2
M3
M4
M5
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
28
29
30
31
32
33
34
35
36
M2004-01
M2004-11
(Top View)
18
17
16
15
14
13
12
11
10
S_CLOCK
MR
nFOUT
FOUT
GND
N1
N0
VCC
GND
F
EATURES
Ideal for OC-48/192 data clock
Integrated SAW (surface acoustic wave) delay line
VCSO frequency from 300 to 700MHz
(Specify VCSO center frequency at time of order)
Low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz or 50kHz to 80MHz)
Pin-selectable or serially programmed configuration
The M2004-11 adds Hitless Switching with Phase
Build-out (HS/PBO) to ensure SONET/SDH MTIE and
TDEV compliance during reference clock reselection
Reference clock inputs support single-ended
LVCMOS, LVTTL
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input Clock VCSO
1
Output
Freq (MHz) Freq (MHz)
(MHz)
19.44
38.80
77.76
155.52
25.00
625.00
622.08
77.76
155.52
311.04
622.08
156.25
Gigabit Ethernet
OC-12 / 48 /192
Application
Table 1: Example Input / Output Frequency Combinations
Note 1: Specify VCSO center frequency at time of order
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2004-01/-11
REF_CLK1
REF_CLK0
REF_SEL
M Divider
S_DATA
S_CLOCK
S_LOAD
nP_LOAD
N Divider
FOUT
nFOUT
1
VCSO
0
Pin Configuration Register
with
Serial Programming Option
6
M5:0
2
N1:0
Figure 2: Simplified Block Diagram
M2004-01/-11 Datasheet Rev 1.0
M2004-01/-11 Frequency Translation PLL
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
MR
Revised 03Jul2003
Integrated Circuit Systems, Inc.
Communications Modules
w w w. i c s t . c o m
tel (508) 852-5400
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