K7Q321854M-FC13 datasheet, PDF

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K7Q321854M-FC13: DescriptionQDR SRAM, 2MX18, 3ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165; Categorystorage storage; File Size512KB，17 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7Q321854M-FC13 Overview

QDR SRAM, 2MX18, 3ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165

K7Q321854M-FC13 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133.33 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	37748736 bit
Memory IC Type	QDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,2.5 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Minimum standby current	2.4 V
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
Base Number Matches	1

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K7Q323654M

K7Q321854M

Document Title

1Mx36-bit, 2Mx18-bit QDR

SRAM

Preliminary

1Mx36 & 2Mx18 QDR

b4 SRAM

Revision History

Rev. No.

0.0

0.1

0.2

History

1. Initial document.

1. Reserved pin for high density name change from NC to Vss/SA

1. Correct AC timing characteristics( tKHCK of -20part ; 0.0 to 2.0 )

Draft Date

Sep. 5, 2001

Dec. 5, 2001

Oct. 23, 2002

Remark

Advance

Preliminary

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

Oct. 2002

Rev 0.2

K7Q323654M

K7Q321854M

GENERAL DESCRIPTION

Preliminary

1Mx36 & 2Mx18 QDR

b4 SRAM

The K7Q323654M and K7Q321854M are 37,748,736-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.

They are organized as 1,048,576 words by 36bits for K7Q323654M and 2,097,152 words by 18 bits for K7Q321854M.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports

with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram

on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address for read and write are latched on alternate rising edges of the input clock K.

Data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 4-bit sequential for both read and write operations, reguiring tow full clock bus cycles.

Any request that attempts to interrupt a burst operation in progress is ignored.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using R and W for port selection.

Byte write operation is supported with BW

and BW

( BW

and BW

3 )

pins.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7Q323654M and K7Q321854M are implemented with SAMSUNG's high performance 6T CMOS technology and is available

in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

The process continues until all four data are transfered.

Continuous read operations are initiated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7Q323654M and K7Q321854M will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

-5-

Oct. 2002

Rev 0.2

K7Q321854M-FC13 Related Products

	K7Q321854M-FC13	K7Q321854M-FC25	K7Q321854M-FC16	K7Q323654M-FC13	K7Q321854M-FC22	K7Q321854M-FC20	K7Q323654M-FC20	K7Q323654M-FC16	K7Q323654M-FC25	K7Q323654M-FC22
Description	QDR SRAM, 2MX18, 3ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 2MX18, 2ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 2MX18, 2.5ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 1MX36, 3ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 2MX18, 2.2ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 2MX18, 2.2ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 1MX36, 2.2ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 1MX36, 2.5ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 1MX36, 2ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165	QDR SRAM, 1MX36, 2.2ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40
Contacts	165	165	165	165	165	165	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Base Number Matches	1	1	1	1	1	1	1	1	1	1
Maximum access time	3 ns	2 ns	2.5 ns	-	2.2 ns	2.2 ns	2.2 ns	-	2 ns	2.2 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133.33 MHz	250 MHz	166.66 MHz	-	222 MHz	200 MHz	200 MHz	-	250 MHz	222 MHz
I/O type	SEPARATE	SEPARATE	SEPARATE	-	SEPARATE	SEPARATE	SEPARATE	-	SEPARATE	SEPARATE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	-	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	-	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e0	e0	e0	-	e0	e0	e0	-	e0	e0
length	17 mm	17 mm	17 mm	-	17 mm	17 mm	17 mm	-	17 mm	17 mm
memory density	37748736 bit	37748736 bit	37748736 bit	-	37748736 bit	37748736 bit	37748736 bit	-	37748736 bit	37748736 bit
Memory IC Type	QDR SRAM	QDR SRAM	QDR SRAM	-	QDR SRAM	QDR SRAM	QDR SRAM	-	QDR SRAM	QDR SRAM
memory width	18	18	18	-	18	18	36	-	36	36
Number of functions	1	1	1	-	1	1	1	-	1	1
Number of terminals	165	165	165	-	165	165	165	-	165	165
word count	2097152 words	2097152 words	2097152 words	-	2097152 words	2097152 words	1048576 words	-	1048576 words	1048576 words
character code	2000000	2000000	2000000	-	2000000	2000000	1000000	-	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	-	70 °C	70 °C	70 °C	-	70 °C	70 °C
organize	2MX18	2MX18	2MX18	-	2MX18	2MX18	1MX36	-	1MX36	1MX36
Output characteristics	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	-	LBGA	LBGA	LBGA	-	LBGA	LBGA
Encapsulate equivalent code	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	-	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	-	BGA165,11X15,40	BGA165,11X15,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	-	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	-	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	1.5/1.8,2.5 V	1.5/1.8,2.5 V	1.5/1.8,2.5 V	-	1.5/1.8,2.5 V	1.5/1.8,2.5 V	1.5/1.8,2.5 V	-	1.5/1.8,2.5 V	1.5/1.8,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	-	1.4 mm	1.4 mm	1.4 mm	-	1.4 mm	1.4 mm
Minimum standby current	2.4 V	2.4 V	2.4 V	-	2.4 V	2.4 V	2.4 V	-	2.4 V	2.4 V
Maximum supply voltage (Vsup)	2.6 V	2.6 V	2.6 V	-	2.6 V	2.6 V	2.6 V	-	2.6 V	2.6 V
Minimum supply voltage (Vsup)	2.4 V	2.4 V	2.4 V	-	2.4 V	2.4 V	2.4 V	-	2.4 V	2.4 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	-	2.5 V	2.5 V	2.5 V	-	2.5 V	2.5 V
surface mount	YES	YES	YES	-	YES	YES	YES	-	YES	YES
technology	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	-	BALL	BALL	BALL	-	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	-	1 mm	1 mm	1 mm	-	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	15 mm	15 mm	15 mm	-	15 mm	15 mm	15 mm	-	15 mm	15 mm

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