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IDT79RC32V334-100BBG

Description
IC proc 32bit core 100mhz 256bga
Categorysemiconductor    The embedded processor and controller   
File Size452KB,30 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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IDT79RC32V334-100BBG Overview

IC proc 32bit core 100mhz 256bga

IDT
TM
Interprise
TM
Integrated
Communications Processor
79RC32334—Rev. Y
Features
RC32300 32-bit Microprocessor
– Up to 150 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
– Supports big or little endian operation
– MMU with 32 page TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
Local Bus Interface
– Up to 75 MHz operation
– 26-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 512MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 512Mb SDRAM device depths
– Automatic refresh generation
Serial Peripheral Interface (SPI) master mode interface
UART Interface
– Two 16550 compatible UARTs
– Baud rate support up to 1.5 Mb/s
– Modem control signals available on one channel
Memory & Peripheral Controller
– 6 banks, up to 64MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
Block Diagram
EJTAG
In-Circuit Emulator Interface
RISCore32300
RC5000
Enhanced MIPS-II ISA Compatible
Integer CPU
CP0
32-page
TLB
Interrupt Control
Programmable I/O
32-bit Timers
SPI Control
DMA Control
Local
Memory/IO
Control
Dual UART
IPBus
Bridge
2kB
2-set, Lockable
Data Cache
8kB
2-set
Lockable
Instr. Cache
Figure 1 RC32334 Block Diagram
IDT
Peripheral
Bus
PCI Bridge
SDRAM
Control
Note:
This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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©
2004 Integrated Device Technology, Inc.
August 31, 2004
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