PEF 22558 E V1.1-G datasheet, PDF

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PEF 22558 E V1.1-G: DescriptionIC interface E1/T1/J1 lbga-256; Categorysemiconductor Analog mixed-signal IC; File Size247KB，2 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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PEF 22558 E V1.1-G Overview

IC interface E1/T1/J1 lbga-256

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Product Brief

O c t a l F A L C

Eight-channel E1/T1/J1 Framer and

LIU PEF 22558 E

T h e O c t a l F A L C

T M

is the latest addition to Infineon’s market-

leading FALC

family of sophisticated E1/T1/J1 transceivers.

As an eight port E1/T1/J1 framer and Line Interface Unit (LIU), the

OctalFALC is optimized for all kinds of network equipment including Radio

Network Controllers, Node B line cards, and PBX or SDH/SONET

add/drop multiplexers.

The OctalFALC features a unique clock generation unit that accepts any

reference clock between 1.02 and 20 MHz, as well as a very compact

17 x 17 mm PG-LBGA-256 package.

Using the industry-leading OctalFALC reference design support tools,

system developers can shorten design cycles while creating a wide range

of highly flexible, low BOM E1/T1/J1 line cards.

The OctalFALC is highly suited for wireless networks, as well as ISDN PRI,

LAN/WAN and Internet access networks.

Frame Aligners

■

ITU-T G.704 frame alignment/ synthesis for

2048/1544 kbit/s

Programmable frame formats include:

– E 1 - double and CRC4 multi-frame

– T1 - F4, F12 (D4) ext. super frame (ESF),

F72 (SLC96)

Detects and generates LOS, AIS and RAI

alarms

CRC-4 performance monitoring

PRBS generation and monitoring

Scalable system bus data rate

from 1.544 MHz up to 16 MHz

Applications

■

HDLC Controllers

■

Wireless Base Stations

Routers

Multi-service Access Platforms

Digital Loop Carriers

Remote access servers/concentrators

SONET/SDH Add/Drop Multiplexers

■

24 HDLC controllers (three per channel)

including 128-byte FIFO buffers

CAS controller with microprocessor or system

interface serial access

Supports signaling system #7

ANSI T1.403 bit-oriented messages (BOM),

generates periodical performance reports

Analog Line Interfaces

■

Eight independent E1/T1/J1 long haul / short haul LIUs

Software programmable T1/E1/J1

Integrated analog switch for impedance matching or protection switching

Crystal-less wander and jitter attenuation/compensation according

to:

– TR 62411

– ETS-TBR 12/13

Clock generation unit accepts any reference clock from 1.02 MHz to

20 MHz

Programmable transmit pulse shape for flexible pulse generation

Receiver sensitivity values exceed -36 dB at 772 kHz, or -43 dB at

1024 kHz

General Features

■

QuadFALC

compatibility mode

Meets Japanese standards including

JT G.703, 704, 706, I.431

Intel

or Motorola

type 8/16-bit

microcontroller interface

Serial SPI bus and serial SCI bus

Low power (150 mW per channel)

Dual voltage 1.8 V/3.3 V power supply

17 x 17 mm PG-LBGA-256 package with

1.0 mm ball pitch

Operating range from -40°C to 85°C

w w w. i n f i n e o n . c o m / f a l c

Wireline Communications

N e v e r

s t o p

t h i n k i n g .

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