Early TX/RX functions to minimize latency through the
device
•
Optional to use external serial EEPROM configuration
for both KSZ8841-16MQL and KSZ8841-32MQL
•
Single 25MHz reference clock for both PHY and MAC
Network Features
•
•
•
•
•
Fully integrated to comply with IEEE802.3u standards
10BASE-T and 100BASE-TX physical layer support
Auto-negotiation: 10/100Mbps full and half duplex
Adaptive equalizer
Baseline wander correction
Additional Features
In addition to offering all of the features of a Layer 2
controller, the KSZ8841M offers:
•
Dynamic buffer memory scheme
– Essential for applications such as Video over IP
where image jitter is unacceptable
•
Flexible 8-bit, 16-bit, and 32-bit generic host
processor interfaces
•
Micrel LinkMD™ cable diagnostic capabilities to
determine cable length, diagnose faulty cables, and
determine distance to fault
•
Wake-on-LAN functionality
– Incorporates Magic Packet™, network link state,
and wake-up frame technology
•
HP Auto MDI-X™ crossover with disable/enable
option
•
Ability to transmit and receive frames up to 1916
bytes
Applications
•
•
•
•
•
•
•
•
Video Distribution Systems
High-end Cable, Satellite, and IP set-top boxes
Video over IP
Voice over IP (VoIP) and Analog Telephone Adapters
(ATA)
Industrial Control in Latency Critical Applications
Motion Control
Industrial Control Sensor Devices (Temperature,
Pressure, Levels, and Valves)
Security and Surveillance Cameras
Power Modes, Power Supplies, and Packaging
•
Single power supply (3.3V) with 5V tolerant I/O
buffers
•
Enhanced power management feature with power-
down feature to ensure low-power dissipation during
device idle periods
•
Comprehensive LED indicator support for link,
activity, full/half duplex, and 10/100 speed (4 LEDs)
– User programmable
•
Low-power CMOS design
o
o
•
Commercial Temperature Range: 0 C to +70 C
o
o
•
Industrial Temperature Range: –40 C to +85 C
Markets
•
Fast Ethernet
•
Embedded Ethernet
•
Industrial Ethernet
•
Available in 128-pin PQFP and 100-ball LFBGA (128-
pin LQFP optional)
October 2007
2
M9999-102207-1.6
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Ordering Information
Part Number
KSZ8841-16MQL
KSZ8841-32MQL
KSZ8841-16MVL
KSZ8841-32MVL
KSZ8841-16MVLI
KSZ8841-32MVLI
KSZ8841-16MBL
KSZ8841-16MBLI
KSZ8841-16MQL-Eval
KSZ8841-16MBL-Eval
Temperature Range
0 C to 70 C
0 C to 70 C
0 C to 70 C
0 C to 70 C
–40 C to +85 C
–40 C to +85 C
0 C to 70 C
–40 C to +85 C
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Package
128-Pin PQFP
128-Pin PQFP
128-Pin LQFP
128-Pin LQFP
128-Pin LQFP
128-Pin LQFP
100-Ball LFBGA
100-Ball LFBGA
Evaluation Board for the KSZ8841-16MQL
Evaluation Board for the KSZ8841-16MBL
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Date
06/30/05
08/08/05
10/04/05
11/01/05
03/31/06
4/10/07
10/22/07
Summary of Changes
First released Preliminary Information.
Updated General Description, Functional Diagram, Pin Description and Features.
Added this Revision History Table and Loopback support sections.
Update Power Saving bit description in P1PHYCTRL and P1SCSLMD registers.
Updated Figure 12/13/14 Asynchronous Timing and Table 16/17/18 parameters, PQFP
package information.
Added QMU RX Flow Control High Watermark QRFCR register and updated body text
Improve the ARDY low time in read cycle to 40 ns and in write cycle to 50 ns during QMU
data register access
Add KSZ8841-16MBL 100-Ball BGA package information
October 2007
3
M9999-102207-1.6
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Contents
General Description .............................................................................................................................................................. 1
Features ................................................................................................................................................................................. 2
Network Features ........................................................................................................................................................... 2
Power Modes, Power Supplies, and Packaging............................................................................................................. 2
Ordering Information ............................................................................................................................................................ 3
Revision History .................................................................................................................................................................... 3
Pin Configuration for KSZ8841-16 Chip (8/16-Bit) ........................................................................................................... 10
Ball Configuration for KSZ8841-16 Chip (8/16-Bit) .......................................................................................................... 11
Pin Description for KSZ8841-16 Chip (8/16-Bit) ............................................................................................................... 12
Ball Description for KSZ8841-16 Chip (8/16-Bit) .............................................................................................................. 17
Pin Configuration for KSZ8841-32 Chip (32-Bit) .............................................................................................................. 21
Pin Description for KSZ8841-32 Chip (32-Bit) .................................................................................................................. 22
Power Management ..................................................................................................................................................... 27
Power down ............................................................................................................................................................................... 27
Link Change............................................................................................................................................................................... 27
MDI/MDI-X Auto Crossover........................................................................................................................................................ 29
Auto Negotiation......................................................................................................................................................................... 31
Media Access Control (MAC) Operation ...................................................................................................................... 32
Inter Packet Gap (IPG)............................................................................................................................................................... 32
Late Collision.............................................................................................................................................................................. 32
Bus Interface Unit (BIU)................................................................................................................................................ 33
Physical Data Bus Size .............................................................................................................................................................. 33
Queue Management Unit (QMU).................................................................................................................................. 38
Transmit Queue (TXQ) Frame Format ....................................................................................................................................... 38
Loopback Support ........................................................................................................................................................ 42
Internal I/O Space Mapping ....................................................................................................................................................... 44
Register Map: MAC and PHY ............................................................................................................................................. 52
Bit Type Definition ........................................................................................................................................................ 52
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) ................................................................ 52
Bank 0 Base Address Register (0x00): BAR................................................................................................................ 52
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ........................................... 53
Bank 0 Bus Error Status Register (0x06): BESR ......................................................................................................... 53
Bank 0 Bus Burst Length Register (0x08): BBLR......................................................................................................... 53
Bank 1: Reserved ......................................................................................................................................................... 53
Bank 2 Host MAC Address Register Low (0x00): MARL ............................................................................................. 54
Bank 2 Host MAC Address Register Middle (0x02): MARM ........................................................................................ 54
Bank 2 Host MAC Address Register High (0x04): MARH............................................................................................ 54
Bank 3 On-Chip Bus Control Register (0x00): OBCR .................................................................................................. 55
Bank 3 EEPROM Control Register (0x02): EEPCR ..................................................................................................... 55
Bank 3 Memory BIST Info Register (0x04): MBIR........................................................................................................ 56
Bank 3 Global Reset Register (0x06): GRR................................................................................................................. 56
Bank 3 Power Management Capabilities Register (0x08): PMCR ............................................................................... 56
Bank 3 Wakeup Frame Control Register (0x0A): WFCR ............................................................................................. 57
Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0...................................................................................... 58
Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1...................................................................................... 58
Bank 8 – 15: Reserved ................................................................................................................................................. 62
Bank 16 Transmit Control Register (0x00): TXCR ....................................................................................................... 63
Bank 16 Transmit Status Register (0x02): TXSR......................................................................................................... 63
Bank 16 Receive Control Register (0x04): RXCR........................................................................................................ 64
Bank 16 TXQ Memory Information Register (0x08): TXMIR........................................................................................ 64
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