Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9328MX1
Rev. 7, 12/2006
MC9328MX1
MC9328MX1
Package Information
Plastic Package
Case 1304B-01
(MAPBGA–225)
Ordering Information
See
Table 1 on page 3
1
Introduction
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signals and Connections . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . 22
Functional Description and Application
Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Pin-Out and Package Information . . . . . . . . 96
6 Product Documentation . . . . . . . . . . . . . . . . 98
Contact Information . . . . . . . . . . . . . . . Last Page
The i.MX Family of applications processors provides a
leap in performance with an ARM9™ microprocessor
core and highly integrated system functions. The i.MX
family specifically addresses the requirements of the
personal, portable product market by providing
intelligent integrated peripherals, an advanced processor
core, and power management capabilities.
The MC9328MX1 (i.MX1) processor features the
advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules,
which include a USB device, an LCD controller, and an
MMC/SD host controller, support a suite of peripherals
to enhance portable products seeking to provide a rich
multimedia experience. It is packaged in a 256-contact
Mold Array Process-Ball Grid Array (MAPBGA).
Figure 1
shows the functional block diagram of the
i.MX1 processor.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved.
Introduction
System Control
JTAG/ICE
Bootstrap
Power
Control
CGM
(DPLLx2)
Standard
System I/O
GPIO
Connectivity
MMC/SD
Memory Stick®
Host Controller
SPI 1 and
SPI 2
UART 1
UART 2 & 3
SSI/I2S 1 & 2
I2C
USB Device
SmartCard I/F
Bluetooth
Accelerator
AIPI 1
MC9328MX1
CPU Complex
ARM9TDMI™
PWM
Timer 1 & 2
RTC
Watchdog
I Cache
D Cache
Multimedia
Multimedia
Accelerator
Video Port
Human Interface
Analog Signal
Processor
LCD Controller
VMMU
Interrupt
Controller
Bus
Control
AIPI 2
DMAC
(11 Chnl)
EIM &
SDRAMC
eSRAM
(128K)
Figure 1. i.MX1 Functional Block Diagram
1.1
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Features
ARM920T™ Microprocessor Core
AHB to IP Bus Interfaces (AIPIs)
External Interface Module (EIM)
SDRAM Controller (SDRAMC)
DPLL Clock and Power Control Module
Three Universal Asynchronous Receiver/Transmitters (UART 1, UART 2, and UART3)
Two Serial Peripheral Interfaces (SPI1 and SPI2)
Two General-Purpose 32-bit Counters/Timers
Watchdog Timer
Real-Time Clock/Sampling Timer (RTC)
LCD Controller (LCDC)
Pulse-Width Modulation (PWM) Module
Universal Serial Bus (USB) Device
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
Memory Stick® Host Controller (MSHC)
Direct Memory Access Controller (DMAC)
Two Synchronous Serial Interfaces and an Inter-IC Sound (SSI1 and SSI2/I
2
S) Module
Inter-IC (I
2
C) Bus Module
Video Port
MC9328MX1 Technical Data, Rev. 7
To support a wide variety of applications, the processor offers a robust array of features, including the following:
2
Freescale Semiconductor
Introduction
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General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Analog Signal Processing (ASP) Module
Bluetooth™ Accelerator (BTA)
Multimedia Accelerator (MMA)
Power Management Features
Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O
256-pin MAPBGA Package
1.2
Target Applications
The i.MX1 processor is targeted for advanced information appliances, smart phones, Web browsers,
based
on the popular Palm OS platform
, and messaging applications
such as wireless cellular products, including the
Accompli
TM
008 GSM/GPRS interactive communicator
.
1.3
Ordering Information
Table 1. Ordering Information
Package Type
256-lead MAPBGA
Frequency
200 MHz
Temperature
0°C to 70°C
-30°C to 70°C
150 MHz
0°C to 70°C
-30°C to 70°C
-40°C to 85°C
Solderball Type
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Order Number
MC9328MX1VM20(R2)
MC9328MX1DVM20(R2)
MC9328MX1VM15(R2)
MC9328MX1DVM15(R2)
MC9328MX1CVM15(R2)
Table 1
provides ordering information.
1.4
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Conventions
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one
is a voltage that corresponds to Boolean true (1) state.
Logic level zero
is a voltage that corresponds to Boolean false (0) state.
To
set
a bit or bits means to establish logic level one.
To
clear
a bit or bits means to establish logic level zero.
A
signal
is an electronic construct whose state conveys or changes in state convey information.
A
pin
is an external physical connection. The same pin can be used to connect a number of signals.
Asserted
means that a discrete signal is in active logic state.
—
Active low
signals change from logic level one to logic level zero.
—
Active high
signals change from logic level zero to logic level one.
This document uses the following conventions:
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
3
Signals and Connections
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Negated
means that an asserted discrete signal changes logic state.
—
Active low
signals change from logic level zero to logic level one.
—
Active high
signals change from logic level one to logic level zero.
LSB means
least significant bit
or
bits,
and MSB means
most significant bit
or
bits.
References to
low and high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or
0x
are hexadecimal.
2
Signals and Connections
Table 2. i.MX1 Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
Table 2
identifies and describes the i.MX1 processor signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
A[24:0]
D[31:0]
EB0
EB1
EB2
EB3
OE
CS [5:0]
ECB
LBA
BCLK (burst clock)
RW
DTACK
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input
signal by external DRAM.
DTACK
signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MX1 processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals
are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
MC9328MX1 Technical Data, Rev. 7
4
Freescale Semiconductor
Signals and Connections
Table 2. i.MX1 Signal Descriptions (Continued)
Signal Name
SDIBA [3:0]
MA [11:10]
MA [9:0]
DQM [3:0]
CSD0
CSD1
Function/Notes
SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on
SDRAM cycles.
SDRAM data enable
SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable
by programming the system control register.
SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by
programming the system control register. By default, CSD1 is selected, so it can be used as boot
chip-select by properly configuring BOOT [3:0] input pins.
SDRAM Row Address Select signal
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
Not Used
Clocks and Resets
EXTAL16M
XTAL16M
EXTAL32K
XTAL32K
CLKO
RESET_IN
RESET_OUT
POR
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut
down.
Crystal output
32 kHz crystal input
32 kHz crystal output
Clock Out signal selected from internal clock signals.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
TDO
TDI
TCK
TMS
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
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