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KMPC8358CZUAGDG

Description
IC mpu pwrquicc II 740-tbga
Categorysemiconductor    The embedded processor and controller   
File Size1MB,95 Pages
ManufacturerFREESCALE (NXP)
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IC mpu pwrquicc II 740-tbga

Freescale Semiconductor
Technical Data
Document Number: MPC8358EEC
Rev. 3, 01/2011
MPC8358E
PowerQUICC II Pro Processor
Revision 2.1 PBGA Silicon
Hardware Specifications
This document provides an overview of the MPC8358E
PowerQUICC II Pro processor revision 2.1 PBGA features,
including a block diagram showing the major functional
components. This device is a cost-effective, highly
integrated communications processor that addresses the
needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
base stations (Node Bs), routers, media gateways, and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane and also has data
plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual,
Rev. 3.
To locate any updates for this document, refer to the
MPC8360E product summary page on our website listed on
the back cover of this document or contact your Freescale
sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . 12
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . 15
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 25
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 59
HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Package and Pin Listings . . . . . . . . . . . . . . . . . 65
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
System Design Information . . . . . . . . . . . . . . . 89
Ordering Information . . . . . . . . . . . . . . . . . . . . 92
Document Revision History . . . . . . . . . . . . . . 94
© 2011 Freescale Semiconductor, Inc. All rights reserved.
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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