CD4098 pulse delay circuit
Source: InternetPublisher:天天都吃好吃的 Keywords: Pulse delay circuit monostable trigger Updated: 2020/09/08
What is shown is that two monostable flip-flops CD4098 (or CD 4528) are cascaded to form a pulse signal delay circuit
. The (IR) and R terminals of A are connected to VDD, and the rising edge trigger is input from the (+1R) terminal, and then a monostable trigger is triggered . The signal is output from the Ql of A
and enters the (+1R) terminal of B. B (TR) is connected to Vss, R is connected to VDD, and B is a "falling edge trigger, then trigger" monostable
flip-flop. So the delayed pulse is obtained from the Q2 terminal of B.
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