Edition 04.2001
Published by Infineon Technologies AG,
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Infineon Technologies AG 4/9/01.
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PEB 20256 E
PEF 20256 E
Revision History:
04.2001
Previous Version:
Preliminary Data Sheet 11.1999
Major changes to document since last version
Page
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Description
Pin Diagram added 16-Port mode
Pin Diagram added 28-Port mode
Remote payload loop block diagram redrawn
DS2
Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER
register as their bit postitions were not correct in the preliminary data sheet.
Swap the postions of TBRTC with TBFTC in Table 8-7, as their column
positions were not correct in the preliminary data sheet
Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD
Fixed typo in IQMASK, replaced ROFD with RFOD
Update voltage min/max information for
Table 9-1 Absolute Maximum
Ratings
Update timing Information for
Table 9-4 DC Characteristics (PCI
Interface Pins)
Update timing Information for
Table 9-5 PCI Clock Characteristics
Update timing Information for
Table 9-6 PCI Interface Signal
Characteristics
Update timing Information for
Table 9-8 Intel Bus Interface Timing
Intel Bus Interface Timing Diagram modified. The setup and hold times for
“LD to LRDY” was not a valid timing parameter. Instead, the setup and hold
parameters for “LD to LRD” were specified.
Update timing Information for
Table 9-9 Intel Bus Interface Timing
(Master Mode)
Timing parameter (setup time) 67a was changed from “LD to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
Timing parameter (hold time) 67b was changed from “LD to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
Update timing Information for
Table 9-10 Motorola Bus Interface Timing
Update timing Information for
Table 9-11 Motorola Bus Interface Timing
(Master Mode)
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Data Sheet
4
04.2001
Microcontroller MCU
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