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www.fairchildsemi.com
KA7630/KA7631
Fixed Multi-Output Regulator
Features
• Output Currents up to 0.5A (Output1 & 2)
• Output Current up to 1A with External Transistor
(Output3)
• Fixed Precision Output 1 Voltage 5.1V ±2%
• Fixed Precision Output 2 Voltage 8V ±2% (KA7630)
• Fixed Precision Output 2 Voltage 9V ±2% (KA7631)
• Control Signal Generator for Output 3 Voltage (12V ±2%)
• Reset Facility for Output Voltage1
• Output 2,3 with Disable by TTL Input
• Current Limit Protection at Each Output
• Thermal Shut Down
Description
The KA7630/KA7631 is a multi-output positive voltage
regulator designed to provide fixed precision output voltages
of 5.1V, 8V (7630) / 9V(7631) at current up to 0.5Aand 12V
at current up to 1A with external PNP transistor.
An internal reset circuit generates a reset pulse when the
output 1 decreases below the regulated value. Output2 & 3
can be disabled by TTL input. Protection features include
over voltage protection, short circuit protection and thermal
shutdown.
10-SIP H/S
Internal Block Diagram
Vin1
1
10uA
3
Cd
100nF
RESET
Vsys
6
-
+
SW
Thermal
Shut Down
OVP
Bandgap
Reference
Vin2
2
OVP
Vin1
2.5V
DEL.CAP
+
-
SCP
9 Output 1
-
+
50mV
Vin2
10K
A614 "Y"
Control
10
Output3
7
-
+
SCP
+
-
+
-
Output 2,3
1.4V
SCP
8 Output 2
5
GND
4
Disable
Rev. 1.0.1
©2002 Fairchild Semiconductor Corporation
KA7630/KA7631
Absolute Maximum Ratings
Parameter
DC Input Voltage
Disable Input Voltage
Output Current
Power Dissipation
Junction Temperature
Operating Temperature
Symbol
Vin
Vc
Io
Pd
Tj
Topr
Value
20
20
0.5
1.5
+150
0 ~ +125
Unit
V
V
A
W
°C
°C
Remark
-
-
-
No Heatsink
-
-
Electrical Characteristics(KA7630)
(Refer to test circuit Vin1=7.5V ,Vin2=10.5V ,Tj = +25°C, unless otherwise specified)
Parameter
Output Voltage 1
Symbol
Vo1
Conditions
Io1 = 10mA
7.5V<Vin1<14V
5mA < Io1< 500mA
Io2 = 10mA
10.5V < Vin2< 18V
5mA < Io2 < 500mA
Io1,2 = 500mA
7.5V < Vin1<14V
10.5V < Vin2 < 18V
Io1,2 = 200mA
5mA < Io1< 500mA
5mA < Io2< 500mA
Vsys=13V, Io3=100mA
13V< Vin2 < 18V, Io3 =100mA
5mA < Io3 < 1A
Cd = 100nF, Note1
I6 = 5mA
V6 = 10V
0°C <Tj < +125°C , Note2
Vin1 = 7.5V ,Vin2 = 10.5V
Output 2 Active
Output 2 Disabled
0V < Vdis < 7V
Note 2
Io1 = 10mA, Output2 Disabled
K = Vo1
Note1
Min.
5
4.9
7.84
7.7
-
-
-
11.7
-
-
-
-
-
-
-
0.8
0.8
-100
-
-
K-0.4
20
Typ.
5.1
5.1
8
8
-
-
-
12
-
-
25
-
-
100
-
-
-
-
145
-
K-0.25
50
1.6
2.0
2.0
2
-
2
K -0.1
100
Max.
5.2
5.3
8.16
8.3
2.5
50
80
100
160
12.3
120
250
-
0.4
10
Unit
V
Output Voltage 2
Dropout Output Voltage 1,2
Line Regulation 1,2
Load Regulation 1,2
Output Voltage 3
Line Regulation 3
Load Regulation 3
Reset Pulse Delay
Saturation Voltage in Reset
Condition
Leakage Current at Pin 6
Output Voltage Thermal Drift
Short Circuit Output Current
Disable Voltage High
Disable Voltage Low
Disable Bias Current
Junction Temperature for TSD
Quiescent Current
Reset Threshold Voltage
Reset Threshold Hysteresis
Vo2
Vd1,2
∆Vo
1,2
∆Vo
1,2
Vo3
∆Vo3
∆Vo3
Trd
VrL
IrH
STt
Isc1,2
VdisH
VdisL
Idis
Ttsd
Iq
Vr
Vrth
V
V
mV
mV
V
mV
mV
ms
V
µA
ppm/°C
A
V
V
µA
°C
mA
V
mA
Notes:
1. To check the reset circuit ,the reset output is low to discharge the delay capacitor(=Cd). it’s less than Vo1-0.25V. And the
reset output is high when the delay capacitor voltage linearly increased by the internal current source(10µA) if it’s more than
Vo1- 0.2V. The equation of delay time is same as below. Trd = (Cd
×
2.5) / 10µA
2. These parameters, although guaranteed, are not 100% tested in production.
2
KA7630/KA7631
Electrical Characteristics(KA7631)
(Continued)
(Refer to test circuit Vin1=7.5V ,Vin2=11.5V ,T
j
= +25°C, unless otherwise specified)
Parameter
Output Voltage 1
Symbol
Vo1
Conditions
Io1 = 10mA
7.5V < Vin1 < 14V
5mA < Io1 < 500mA
Io2 = 10mA
11.5V < Vin2 < 18V
5mA < Io2< 500mA
Io1,2 = 500mA
7.5V < Vin1< 14V
11.5V < Vin2< 18V
Io1,2 = 200mA
5mA < Io1< 500mA
5mA < Io2 < 500mA
Vsys =13V, Io3 = 100mA
13V < Vin2 <18V, Io3 =100mA
5mA < Io3 < 1A
Cd = 100nF, Note1
I6 = 5mA
V6 = 10V
0°C < Tj < +125°C , Note2
Vin1 = 7.5V ,Vin2 = 11.5V
Output 2 Active
Output 2 Disabled
0V < Vdis < 7V
Note2
Io1=10mA, Output2 Disabled
K = Vo1
Note1
Min.
5
4.9
8.82
8.65
-
-
-
11.7
-
-
-
-
-
-
-
0.8
0.8
-100
-
-
K-0.4
20
Typ.
5.1
5.1
9
9
-
-
-
12
-
-
25
-
-
100
-
-
-
-
145
-
K-0.25
50
Max.
5.2
5.3
9.18
9.35
2.5
50
80
100
160
12.3
120
250
-
0.4
10
-
1.6
2.0
2.0
2
-
2
K -0.1
100
Unit
V
Output Voltage 2
Dropout Output Voltage 1,2
Line Regulation 1,2
Load Regulation 1,2
Output Voltage 3
Line Regulation 3
Load Regulation 3
Reset Pulse Delay
Saturation Voltage in Reset
Condition
Leakage Current at Pin 6
Output Voltage Thermal Drift
Short Circuit Output Current
Disable Voltage High
Disable Voltage Low
Disable Bias Current
Junction Temperature for TSD
Quiescent Current
Reset Threshold Voltage
Reset Threshold Hysteresis
Vo2
Vd1,2
∆Vo
1,2
∆Vo
1,2
Vo3
∆Vo3
∆Vo3
Trd
VrL
IrH
STt
Isc1,2
VdisH
VdisL
Idis
Ttsd
Iq
Vr
Vrth
V
V
mV
mV
V
mV
mV
ms
V
µA
ppm/°C
A
V
V
µA
°C
mA
V
mA
Notes:
1. To check the reset circuit ,the reset output is low to discharge the delay capacitor(=Cd). if it’s less than Vo1-0.25V. And the
reset output is high when the delay capacitor voltage linearly increased by the internal current source(10µA) if it’s more than
Vo1- 0.2V. The equation of delay time is same as below. Trd = (Cd
×
2.5) / 10µA
2. These parameters, although guaranteed, are not 100% tested in production.
3
KA7630/KA7631
Mechanical Dimensions
Package
Dimensions in millimeters
10-SIP-H/S
3.25
±0.20
0.128
±0.008
#1
1.50
)
0.059
0.50
±0.10
0.020
±0.004
(
25.75
±0.10
1.013
±0.004
26.05
MAX
1.026
#10
1.30
)
0.051
2.54
0.100
1.30
±0.10
0.051
±0.004
1.00
±0.20
0.039
±0.008
7.00
±0.30
0.276
±0.012
8.90
±0.20
0.350
±0.008
13.65
±0.30
0.537
±0.012
16.80
MAX
0.661
(
0.50
±0.10
0.020
±0.004
4
1.65
±0.10
0.065
±0.004
3.80
±0.20
0.150
±0.008
23.86
±0.20
0.939
±0.008
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