CS4384
103 dB, 192 kHz 8-Channel D/A Converter
Features
!
Advanced Multi-bit Delta Sigma Architecture
!
24-bit Conversion
!
Automatic Detection of Sample Rates up to
Description
The CS4384 is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
half-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Follow-
ing this stage is a multi-element switched capacitor
stage and low-pass filter with single-ended analog
outputs.
The CS4384 also has a proprietary DSD processor
which allows for volume control and 50 kHz on-chip fil-
tering without an intermediate decimation stage. It also
offers an optional path for direct DSD conversion by di-
rectly using the multi-element switched capacitor array.
The CS4384 accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.
This product is available in 48-pin LQFP package and is
available in both Automotive (-40° C - +85° C) and
Commercial (-10° C - +70° C) temperature grades. For
full Ordering Information see
page 50.
192 kHz
!
103 dB Dynamic Range
!
-88 dB THD+N
!
Single-Ended Output Architecture
!
Direct Stream Digital Mode
–
–
–
Non-Decimating Volume Control
On-Chip 50 kHz Filter
Matched PCM and DSD Analog Output
Levels
!
Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
!
Selectable Digital Filters
!
Volume Control with 1/2-dB Step Size and Soft
Ramp
!
Low Clock Jitter Sensitivity
!
+5 V Analog Supply, +2.5 V Digital Supply
!
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Level Translator
Hardware Mode or
I
2
C/SPI Software Mode
Control Data
Register/Hardware
Configuration
Internal Voltage
Reference
Reset
Serial Audio Port
Supply = 1.8 V to 5 V
PCM Serial
Audio Input
TDM Serial
Audio Input
DSD Audio
Input
8
Volume
Controls
Digital
Filters
Multi-bit
∆Σ
Modulators
Level Translator
Serial Interface
Switch-Cap
DAC and
Analog Filters
8
Eight Channels
of Single-Ended
Outputs
DSD Processor
-Volume control
-50 kHz filter
External Mute
Control
2
Mute Signals
Advance Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 2005
(All Rights Reserved)
AUGUST '05
DS620A1
CS4384
TABLE OF CONTENTS
1. PIN DESCRIPTION................................................................................................................................. 6
2. CHARACTERISTICS AND SPECIFICATIONS...................................................................................... 8
SPECIFIED OPERATING CONDITIONS .................................................................................................... 8
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8
DAC ANALOG CHARACTERISTICS........................................................................................................... 9
DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED) ........................................................ 10
POWER AND THERMAL CHARACTERISTICS........................................................................................ 10
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 12
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE .................................................. 12
DIGITAL CHARACTERISTICS .................................................................................................................. 13
SWITCHING CHARACTERISTICS - PCM ................................................................................................ 14
SWITCHING CHARACTERISTICS - DSD................................................................................................. 15
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT.................................................... 16
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT ............................................... 17
3. APPLICATIONS ................................................................................................................................... 20
3.1 Master Clock.................................................................................................................................. 20
3.2 Mode Select.................................................................................................................................. 21
3.3 Digital Interface Formats ............................................................................................................... 22
3.3.1 OLM #1 ................................................................................................................................ 23
3.3.2 OLM #2 ................................................................................................................................ 23
3.3.3 OLM #3 ................................................................................................................................ 24
3.3.4 OLM #4 ................................................................................................................................ 24
3.3.5 TDM ..................................................................................................................................... 25
3.4 Oversampling Modes..................................................................................................................... 25
3.5 Interpolation Filter .......................................................................................................................... 25
3.6 De-Emphasis ................................................................................................................................. 26
3.7 ATAPI Specification ....................................................................................................................... 26
3.8 Direct Stream Digital (DSD) Mode................................................................................................. 27
3.9 Grounding and Power Supply Arrangements ................................................................................ 28
3.9.1 Capacitor Placement............................................................................................................ 28
3.10 Analog Output and Filtering ......................................................................................................... 28
3.11 The MUTEC Outputs ................................................................................................................... 29
3.12 Recommended Power-Up Sequence .......................................................................................... 29
3.12.1 Hardware Mode.................................................................................................................. 29
3.12.2 Software Mode ................................................................................................................... 30
3.13 Recommended Procedure for Switching Operational Modes...................................................... 30
3.14 Control Port Interface .................................................................................................................. 30
3.14.1 MAP Auto Increment .......................................................................................................... 30
3.14.2 I²C Mode ............................................................................................................................ 30
3.14.3 SPI™ Mode........................................................................................................................ 32
3.15 Memory Address Pointer (MAP) ................................................................................................. 32
3.15.1 INCR (Auto Map Increment Enable) .................................................................................. 32
3.15.2 MAP4-0 (Memory Address Pointer) ................................................................................... 32
4. REGISTER QUICK REFERENCE ....................................................................................................... 33
5. REGISTER DESCRIPTION .................................................................................................................. 34
5.1 Chip Revision (address 01h) ......................................................................................................... 34
5.1.1 Part Number ID (part) [Read Only]....................................................................................... 34
5.2 Mode Control 1 (address 02h) ....................................................................................................... 34
5.2.1 Control Port Enable (CPEN) ................................................................................................ 34
5.2.2 Freeze Controls (FREEZE) .................................................................................................. 35
5.2.3 PCM/DSD Selection (DSD/PCM)......................................................................................... 35
2
DS620A1
CS4384
5.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 35
5.2.5 Power Down (PDN).............................................................................................................. 35
5.3 PCM Control (address 03h) ........................................................................................................... 35
5.3.1 Digital Interface Format (DIF)............................................................................................... 35
5.3.2 Functional Mode (FM) .......................................................................................................... 36
5.4 DSD Control (address 04h) ........................................................................................................... 36
5.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 36
5.4.2 Direct DSD Conversion (DIR_DSD)..................................................................................... 37
5.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 37
5.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 37
5.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 37
5.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 38
5.5 Filter Control (address 05h) ........................................................................................................... 38
5.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 38
5.6 Invert Control (address 06h) .......................................................................................................... 38
5.6.1 Invert Signal Polarity (INV_xx) ............................................................................................. 38
5.7 Group Control (address 07h) ......................................................................................................... 38
5.7.1 Mutec Pin Control (MUTEC) ................................................................................................ 38
5.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 39
5.7.3 Single Volume Control (SNGLVOL) ..................................................................................... 39
5.8 Ramp and Mute (address 08h) ...................................................................................................... 39
5.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 39
5.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 40
5.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ................................................... 40
5.8.4 PCM Auto-Mute (PAMUTE) ................................................................................................. 40
5.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 40
5.8.6 MUTE Polarity and DETECT (MUTEP1:0)........................................................................... 41
5.9 Mute Control (address 09h) ........................................................................................................... 41
5.9.1 Mute (MUTE_xx) .................................................................................................................. 41
5.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h).............................................................................. 41
5.10.1 De-Emphasis Control (PX_DEM1:0).................................................................................. 41
5.11 ATAPI Channel Mixing and Muting (ATAPI) ................................................................................ 42
5.12 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) ........................................... 43
5.12.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 43
5.13 PCM Clock Mode (address 16h).................................................................................................. 43
5.13.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 43
6. FILTER RESPONSE PLOTS ............................................................................................................... 44
7. REFERENCES...................................................................................................................................... 48
8. PARAMETER DEFINITIONS................................................................................................................ 48
9. PACKAGE DIMENSIONS .................................................................................................................... 49
10. ORDERING INFORMATION .............................................................................................................. 50
11. REVISION HISTORY ......................................................................................................................... 50
DS620A1
3
CS4384
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing...................................................................................................... 14
Figure 2. TDM Serial Audio Interface Timing ............................................................................................. 14
Figure 3. Direct Stream Digital - Serial Audio Input Timing........................................................................ 15
Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................... 15
Figure 5. Control Port Timing - I²C Format................................................................................................. 16
Figure 6. Control Port Timing - SPI Format................................................................................................ 17
Figure 7. Typical Connection Diagram, Software Mode............................................................................. 18
Figure 8. Typical Connection Diagram, Hardware Mode ........................................................................... 19
Figure 9. Format 0 - Left-Justified up to 24-bit Data .................................................................................. 22
Figure 10. Format 1 - I²S up to 24-bit Data ................................................................................................ 22
Figure 11. Format 2 - Right-Justified 16-bit Data ....................................................................................... 22
Figure 12. Format 3 - Right-Justified 24-bit Data ....................................................................................... 22
Figure 13. Format 4 - Right-Justified 20-bit Data ....................................................................................... 22
Figure 14. Format 5 - Right-Justified 18-bit Data ....................................................................................... 23
Figure 15. Format 8 - One Line Mode 1..................................................................................................... 23
Figure 16. Format 9 - One Line Mode 2..................................................................................................... 23
Figure 17. Format 10 - One Line Mode 3................................................................................................... 24
Figure 18. Format 11 - One Line Mode 4................................................................................................... 24
Figure 19. Format 12 - TDM Mode............................................................................................................. 25
Figure 20. De-Emphasis Curve.................................................................................................................. 26
Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) ............................................................... 26
Figure 22. DSD Phase Modulation Mode Diagram .................................................................................... 27
Figure 23. Full-Scale Output ...................................................................................................................... 28
Figure 24. Recommended Output Filter..................................................................................................... 28
Figure 25. Recommended Mute Circuitry .................................................................................................. 29
Figure 26. Control Port Timing, I²C Mode .................................................................................................. 31
Figure 27. Control Port Timing, SPI Mode ................................................................................................. 32
Figure 28. Single-Speed (fast) Stopband Rejection................................................................................... 44
Figure 29. Single-Speed (fast) Transition Band ......................................................................................... 44
Figure 30. Single-Speed (fast) Transition Band (detail) ............................................................................. 44
Figure 31. Single-Speed (fast) Passband Ripple ....................................................................................... 44
Figure 32. Single-Speed (slow) Stopband Rejection ................................................................................. 44
Figure 33. Single-Speed (slow) Transition Band........................................................................................ 44
Figure 34. Single-Speed (slow) Transition Band (detail)............................................................................ 45
Figure 35. Single-Speed (slow) Passband Ripple...................................................................................... 45
Figure 36. Double-Speed (fast) Stopband Rejection ................................................................................. 45
Figure 37. Double-Speed (fast) Transition Band........................................................................................ 45
Figure 38. Double-Speed (fast) Transition Band (detail)............................................................................ 45
Figure 39. Double-Speed (fast) Passband Ripple...................................................................................... 45
Figure 40. Double-Speed (slow) Stopband Rejection ................................................................................ 46
Figure 41. Double-Speed (slow) Transition Band ...................................................................................... 46
Figure 42. Double-Speed (slow) Transition Band (detail) .......................................................................... 46
Figure 43. Double-Speed (slow) Passband Ripple .................................................................................... 46
Figure 44. Quad-Speed (fast) Stopband Rejection .................................................................................... 46
Figure 45. Quad-Speed (fast) Transition Band .......................................................................................... 46
Figure 46. Quad-Speed (fast) Transition Band (detail) .............................................................................. 47
Figure 47. Quad-Speed (fast) Passband Ripple ........................................................................................ 47
Figure 48. Quad-Speed (slow) Stopband Rejection................................................................................... 47
Figure 49. Quad-Speed (slow) Transition Band......................................................................................... 47
Figure 50. Quad-Speed (slow) Transition Band (detail)............................................................................. 47
Figure 51. Quad-Speed (slow) Passband Ripple....................................................................................... 47
4
DS620A1
CS4384
LIST OF TABLES
Table 1. Single-Speed Mode Standard Frequencies ................................................................................
Table 2. Double-Speed Mode Standard Frequencies...............................................................................
Table 3. Quad-Speed Mode Standard Frequencies .................................................................................
Table 4. PCM Digital Interface Format, Hardware Mode Options.............................................................
Table 5. Mode Selection, Hardware Mode Options ..................................................................................
Table 6. Direct Stream Digital (DSD), Hardware Mode Options ...............................................................
Table 7. Digital Interface Formats - PCM Mode........................................................................................
Table 8. Digital Interface Formats - DSD Mode ........................................................................................
Table 9. ATAPI Decode ............................................................................................................................
Table 10. Example Digital Volume Settings ..............................................................................................
20
20
20
21
21
21
36
37
42
43
DS620A1
5
京公网安备 11010802033920号
EEWORLD
