500R18N680FV4 datasheet, PDF - EEWORLD Datasheet

500R18N680FV4: DescriptionCeramic Capacitor, Multilayer, Ceramic, 50V, 1% +Tol, 1% -Tol, NP0, -/+30ppm/Cel TC, 0.000068uF, 1206,; CategoryPassive components capacitor; File Size28KB，1 Pages; ManufacturerJohanson Dielectrics; Environmental Compliance

Download Datasheet Parametric View All

500R18N680FV4 Overview

Ceramic Capacitor, Multilayer, Ceramic, 50V, 1% +Tol, 1% -Tol, NP0, -/+30ppm/Cel TC, 0.000068uF, 1206,

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	893647312
package instruction	, 1206
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	0
capacitance	0.000068 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	1.27 mm
JESD-609 code	e3
length	3.43 mm
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	1%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	BULK
positive tolerance	1%
Rated (DC) voltage (URdc)	50 V
size code	1206
surface mount	YES
Temperature characteristic code	C0G
Temperature Coefficient	30ppm/Cel ppm/°C
Terminal surface	Matte Tin (Sn) - with Nickel (Ni) barrier
Terminal shape	WRAPAROUND
width	1.83 mm

Authoritative sources refute new arguments for analog circuit design: At the International Solid-State Circuits Conference (ISSCC), a group of analog experts, mostly university professors and researchers, specifically refuted the argument that the "golden age" of analog...; fighting Analog electronics

Several questions about FOR loop statement: FOR loop statements can be used in VERILOG . VHDL simulation statements, but cannot be synthesized by synthesizers. As far as I know, VHDL syntax FOR I IN 0 TO 30 LOOP loop statements are supported by...; eeleader FPGA/CPLD

Analysis of fatal problems in the life of high-brightness LEDs: 1. Heat management is the main problem in high-brightness LED applications 　　Since the p-type doping of III-nitrides is limited by the solubility of Mg acceptors and the high activation energy of hole...; 探路者 LED Zone

Problems using barcode scanner in embedded Linux: The barcode scanner has a USB interface, so the USB driver has been installed. There will be a prompt after plugging in the scanner, but how to display the read barcode? Normally in Windows or Linux s...; shizibaihe Linux and Android

How to call a subroutine in Verilog?: How to call a subroutine in Verilog:Can I call other subroutines in Verilog? How can I do it?I want to add some other processing to the original program, and I want to use the method of calling subrou...; BEN121 FPGA/CPLD

I use STC89LE58RD+ chip, when LCD display, if any key is pressed, there will be garbled characters, please help!: I use STC89LE58RD+ chip. When LCD displays, there will be garbled characters if a key is pressed. Please help! Keyboard scanning uses T1, LCD operation is in the main loop, and there is an external in...; shinecx2 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components