Power Dissipation.............................................................................................................................................Internally Limited
Peak Transient Voltage (46V Load Dump) .................................................................................................................-50V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature .............................................................................................................................................-40¡C to 150¡C
Storage Temperature...............................................................................................................................................-55¡C to 150¡C
Lead Temperature Soldering Wave Solder (through hole styles only) ..........................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ..........................................60 sec. max above 183¡C, 230¡C peak
Electrical Characteristics: T
A
= -40ûC to +125ûC, T
J
= -40ûC to +150ûC, V
IN
= 6 to 26V, I
O
=5 to 500mA,
R
RESET
= 4.7k½ to V
CC,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Output Stage (V
OUT
)
Output Voltage
Dropout Voltage
Supply Current
I
OUT
= 500mA
I
OUT
² 10mA
I
OUT
² 100mA
I
OUT
² 500mA
V
IN
= 6 to 26V, I
OUT
= 50mA
I
OUT
= 50 to 500mA, V
IN
= 14V
f = 120Hz, V
IN
= 7 to 17V,
I
OUT
= 250mA
54
0.75
32
V
OUT
² 5.5V
V
OUT
³ -0.6V, 10½ Load
1% Duty Cycle, T < 100ms,
10½ Load
Guaranteed by Design
150
-15
95
-30
-80
180
210
4.85
5.00
0.35
2
6
55
5
10
75
1.20
40
5.15
0.60
7
12
100
50
50
V
V
mA
Line Regulation
Load Regulation
Ripple Rejection
Current Limit
Overvoltage Shutdown
Maximum Line Transient
Reverse Polarity Input
Voltage DC
Reverse Polarity Input
Voltage Transient
Thermal Shutdown
s
RESET and Delay Functions
Delay Charge Current
RESET Threshold
RESET Hysteresis
Delay Threshold
Delay Hysteresis
RESET Output Voltage Low
RESET Output Leakage
Current
Delay Capacitor
Discharge Voltage
Delay Time
mV
mV
dB
A
V
V
V
V
¡C
V
Delay
= 2V
V
OUT
Increasing, V
RT(ON)
V
OUT
Decreasing, V
RT(OFF)
V
RH
= V
RT(ON)
- V
RT(OFF)
Charge, V
DC(HI)
Discharge, V
DC(LO)
1V < V
OUT
< V
RTL
, 3k½ to V
OUT
V
OUT
> V
RT(ON)
Discharge Latched ÒONÓ,
V
OUT
> V
RT
C
Delay
= 0.1µF* (Note 1)
5
4.65
4.50
150
3.25
2.85
200
10
4.90
4.70
200
3.50
3.10
400
0.1
0
0.2
15
V
OUT
- 0.01
V
OUT
- 0.15
250
3.75
3.35
800
0.4
10
0.5
48
µA
V
V
mV
V
V
mV
V
µA
V
ms
16
32
Delay Time =
C
Delay
´
V
Delay
Threshold Charge
= C
Delay
x 3.2 x 10
5
(typ)
I
Charge
Note 1: assumes ideal capacitor
2
CS8126, -1, -2
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
5 Lead TO-220
8126-1 8126-2
1
2
3
4
5
1
5
3
4
2
7Lead
D
2
PAK
1
2
4
5
6
16 Lead
SOIC Wide
1
16
11
8
6
V
IN
V
OUT
Gnd
Delay
RESET
Unregulated supply voltage to IC.
Regulated 5V output.
Ground connection.
Timing capacitor for RESET function.
CMOS/TTL compatible output lead. RESET goes low
after detection of any error in the regulated output or
during power up.
Remote sensing of output voltage.
No Connection.
3
7
14
2, 3, 4, 5, 7, 9,
10, 12, 13, 15
V
OUT(SENSE)
NC
Typical Performance Characteristics
I
CQ
vs. V
IN
over Temperature
R
LOAD
= 25W
I
CQ
vs. V
IN
over R
LOAD
Room Temp.
55.0
50.0
45.0
40.0
ICQ (mA)
30.0
25.0
20.0
15.0
10.0
5.0
0.0
125ûC
25ûC
ICQ (mA)
35.0
-40ûC
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
V
IN
(V)
120.0
110.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
V
IN
(V)
R
load
= 6.67
R
load
= 10
R
load
= 25
R
load
= NO LOAD
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
V
OUT
vs V
IN
over Temperature
R
LOAD
= 25W
V
OUT
vs. V
IN
over R
LOAD
Room Temp.
5.5
5.0
4.5
4.0
3.5
V
OUT
(V)
V
OUT
(V)
5.5
5.0
4.5
4.0
3.5
125ûC
Rload = 6.67
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Rload =
NO LOAD
Rload = 10
25ûC
-40ûC
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
V
IN
(V)
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
V
IN
(V)
3
CS8126, -1, -2
Typical Performance Characteristics: continued
Line Regulation vs. Output Current over Temperature
100
80
60
Load Regulation (mV)
Line Regulation (mV)
V
IN
6-26V
Load Regulation vs. Output Current over Temperature
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
V
IN
= 14V
TEMP = 125ûC
TEMP = 25ûC
TEMP = -40ûC
40
20
0
-20
-40
-60
-80
-100
0
100
200
300
400
500
600
700
800
Output Current (mA)
TEMP = 125ûC
TEMP = 25ûC
TEMP = 40ûC
0
100
200
300
400
500
600
700
800
Output Current (mA)
Dropout Voltage vs. Output Current over Temperature
900
800
Quiescent Current (mA)
Dropout Voltage (mV)
Quiescent Current vs. Output Current over Temperature
100
90
80
70
60
50
40
30
20
10
0
V
IN
= 14V
25ûC
125ûC
700
600
500
400
300
200
100
0
0
100
200
300
400
500
600
700
800
Output Current (mA)
-40ûC
125ûC
25ûC
-40ûC
0
100
200
300
400
500
600
700
800
Output Current (mA)
Ripple Rejection
I
OUT
= 250mA
Output Capacitor ESR
10
3
10
2
90
80
70
Rejection (dB)
C
OUT
= 10mF, ESR = 1 & 0.1mF,
ESR = 0
10
1
ESR (ohms)
C
OUT
= 47/68mF
Stable Region
60
50
40
30
20
10
0
10
0
10
0
10
-1
10
-2
C
OUT
= 10mF, ESR = 1W
C
OUT
= 47mF
C
OUT
= 68mF
C
OUT
= 10mF, ESR = 10W
10
-3
7
8
10
1
10
2
10
3
10
4
10
5
10
6
10
10
10
-4
10
0
10
1
10
2
10
3
Freq. (Hz)
Output Current (mA)
4
CS8126, -1, -2
RESET Circuit Waveform
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
V
OUT
V
RT(ON)
V
RT(OFF)
V
RH
RESET
(1)
(2)
V
RL
(3)
t
Delay
Delay
V
DH
V
DC(HI)
V
DC(LO)
(2)
V
DIS
Circuit Description
The CS8126 RESET function, has hysteresis on both the
Reset and Delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when the output
voltage falls below V
RT(OFF)
, causes the RESET output tran-
sistor to be in the ON (saturation) state. When the output
voltage rises above V
RT(ON)
, this circuit permits the RESET
output transistor to go into the OFF state if allowed by
the RESET Delay circuit.
RESET Delay Circuit
This circuit provides a programmable (by external capaci-
tor) delay on the RESET output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above V
RT(ON)
. Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage falls below V
RT(OFF)
. The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled RESET pulse is generated following
detection of an error condition. The circuit allows
the RESET output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
V
DC(H1)
.
The Delay time for the RESET function is calculated from
the formula:
C
Delay
´
V
Delay
Threshold
Delay time =
I
Charge
Delay time = C
Delay
´
3.2
´
10
5
If C
Delay
= 0.1µF, Delay time (ms) = 32ms ± 50%: i.e. 16ms
to 48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
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