93LCS56/66
2K/4K 2.5V CMOS Serial EEPROM with Software Write Protect
FEATURES
• Single supply with programming operation down
to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 5
µ
A standby current (typical) at 3.0V
• x16 memory organization
- 128x16 (93LCS56)
- 256x16 (93LCS66)
• Software write protection of user defined memory
space
• Self timed erase and write cycles
• Automatic ERAL before WRAL
• Power on/off data protection
• Industry standard 3-wire serial I/O
• Device status signal during E/W
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC packages
• Commercial:
0˚C
to +70˚C
• Industrial:
-40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 93LCS56/66 are low volt-
age Serial Electrically Erasable PROMs with memory
capacities of 2K bits/4K bits respectively. A write protect
register is included in order to provide a user defined
region of write protected memory. All memory locations
greater than or equal to the address placed in the write
protect register will be protected from any attempted write
or erase operation. It is also possible to protect the
address in the write protect register permanently by using
a one time only instruction (PRDS). Any attempt to alter
data in a register whose address is equal to or greater
than the address stored in the protect register will be
aborted. Advanced CMOS technology makes this device
ideal for low power non-volatile memory applications.
BLOCK DIAGRAM
V
CC
V
SS
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
OUTPUT
BUFFER
DATA REGISTER
DI
PRE
PE
CS
MODE
DECODE
LOGIC
DO
CLK
CLOCK
GENERATOR
PACKAGE TYPE
SOIC
NC
CS
DIP
CS
CLK
DI
DO
1
2
3
4
93LCS56
93LCS66
8
7
6
5
V
CC
PRE
PE
V
SS
CS
CLK
DI
DO
1
2
3
4
93LCS56
93LCS66
SOIC
8
7
6
5
V
CC
PRE
PE
V
SS
CLK
NC
DI
DO
NC
1
2
3
4
5
6
7
93LCS56
93LCS66
14
13
12
11
10
9
8
NC
V
CC
PRE
NC
PE
V
SS
NC
©
1995 Microchip Technology Inc.
DS11181C-page 1
93LCS56/66
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
CS
CLK
DI
DO
V
SS
PE
PRE
V
CC
PIN FUNCTION TABLE
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Protect Register Enable
Power Supply
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
.....-0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins..................................... 4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
V
CC
= +2.5V to +6.0V
Commercial(C):
Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚C to +85˚C
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Symbol
V
IH
V
IL
V
OL
1
V
OL
2
V
OH
1
V
OH
2
I
LI
I
LO
C
IN
, C
OUT
I
CC
Write
I
CC
Read
Min
2.0
-0.3
—
—
2.4
V
CC
-0.2
-10
-10
—
—
—
—
—
250
250
50
0
250
100
100
0
500
100
100
—
—
Max
V
CC
+1
0.8
0.4
0.2
—
—
10
10
7
3
1
500
100
30
2
1
—
—
—
—
—
—
—
—
—
—
—
400
100
500
Units
V
V
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
µ
A
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
≥
2.5V
V
CC
≥
2.5V
Conditions
I
OL
= 2.1 mA; V
CC
= 4.5V
I
OL
= 100
µ
A; V
CC
= 2.5V
I
OH
= -400
µ
A; V
CC
= 4.5V
I
OH
= -100
µ
A; V
CC
= 2.5V
V
IN
= 0.1V to V
CC
V
OUT
= 0.1V to Vcc
V
IN
/V
OUT
= 0V (Note 1 & 3)
Tamb = +25˚C; F
CLK
= 1 MHz
F
CLK
= 2 MHz; V
CC
= 3.0V (Note 3)
F
CLK
= 2 MHz; V
CC
= 6.0V
F
CLK
= 1 MHz; V
CC
= 3.0V
CLK = CS = 0V; V
CC
= 6.0V
CLK = CS = 0V; V
CC
= 3.0V
V
CC
≥
4.5V
V
CC
< 4.5V
Standby current
Clock frequency
Clock high time
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
PRE setup time
PE setup time
PRE hold time
PE hold time
Data input setup time
Data input hold time
Data output delay time
Data output disable time
Status valid time
I
CCS
F
CLK
T
CKH
T
CKL
T
CSS
T
CSH
T
CSL
T
PRES
T
PES
T
PREH
T
PEH
T
DIS
T
DIH
T
PD
T
CZ
T
SV
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
CL=100 pF
CL=100 pF (Note 3)
CL=100 pF
©
1995 Microchip Technology Inc.
DS11181C-page 2
93LCS56/66
V
CC
= +2.5V to +6.0V
Commercial(C):
Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚C to +85˚C
Parameter
Program cycle time
Symbol
T
WC
T
EC
T
WL
Min
Max
10
15
30
Units
ms
ms
ms
ERAL mode
WRAL mode
Conditions
ERASE/WRITE mode (Note 2)
Note 1: This parameter is tested at Tamb = 25˚C and F
CLK
= 1 MHz.
Note 2: Typical program cycle time is 4 ms per word.
Note 3: This parameter is periodically sampled and not 100% tested.
TABLE 1-3:
INSTRUCTION SET FOR 93LCS56*/66
93LCS56/66 (x 16 organization)
Instruction SB Opcode
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
PRREAD
PREN
1
1
1
1
1
1
1
1
1
10
00
11
00
01
00
00
10
00
Address
A7 - A0*
11XXXXXX
A7 - A0*
10XXXXXX
A7 - A0*
01XXXXXX
00XXXXXX
XXXXXXXX
11XXXXXX
Data In
—
—
—
—
D15 - D0
D15 - D0
—
—
—
Data Out
D15-D0
High-Z
(RDY/
BSY)
(RDY/
BSY)
(RDY/
BSY)
(RDY/
BSY)
High-Z
A7-A0
High-Z
PRE
0
0
PE
X
1
1
Comments
Reads data stored in memory, start-
ing at specified address.
Erase/Write Enable must precede all
programming modes.
Erase data at specified address
location if address is unprotected.
Erase all registers to “FF”. Valid only
when Protect Register is cleared.
Writes register if address is unpro-
tected.
Writes all registers. Valid only when
Protect Register is cleared.
Erase/Write Disable deactivates all
programming instructions.
Reads address stored in Protect
Register.
Must immediately precede
PRCLEAR, PRWRITE and PRDS
instructions.
Clears the Protect Register such that
all data are NOT write-protected.
Programs address into Protect Reg-
ister. Thereafter, memory addresses
greater than or equal to the address
in Protect Register are write-pro-
tected.
ONE TIME ONLY instruction after
which the address in the Protect
Register cannot be altered.
0
0
0
0
1
1
1
1
1
X
X
1
PRCLEAR
PRWRITE
1
1
11
01
11111111
A7 - A0*
—
—
(RDY/
BSY)
(RDY/
BSY)
1
1
1
1
PRDS
1
00
00000000
—
(RDY/
BSY)
1
1
*Address A7 bit is a “don’t care” on 93LCS56.
©
1995 Microchip Technology Inc.
DS11181C-page 3
93LCS56/66
2.0
FUNCTIONAL DESCRIPTION
3.0
READ
The 93LCS56/66 is organized as 128/256 registers by
16 bits. Instructions, addresses and write data are
clocked into the DI pin on the rising edge of the clock
(CLK). The DO pin is normally held in a high-Z state
except when reading data from the device, or when
checking the ready/busy status during a programming
operation. The ready/busy status can be verified dur-
ing an Erase/Write operation by polling the DO pin; DO
low indicates that programming is still in progress,
while DO high indicates the device is ready. The DO
will enter the high-Z state on the falling edge of the CS.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit output string. The output
data bits will toggle on the rising edge of the CLK and
are stable after the specified time delay (T
PD
).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next regis-
ter and output sequentially.
4.0
ERASE/WRITE ENABLE AND
DISABLE
2.1
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and
PRDS). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
The 93LCS56/66 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
The PE pin MUST be held “high” while loading the
EWEN instruction. Once the EWEN instruction is exe-
cuted, programming remains enabled until an EWDS
instruction is executed or V
CC
is removed from the
device. To protect against accidental data disturb, the
EWDS instruction can be used to disable all Erase/
Write functions and should follow all programming
operations. Execution of a READ instruction is inde-
pendent of both the EWEN and EWDS instructions.
5.0
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle. The PE pin MUST be latched “high” during load-
ing the ERASE instruction but becomes a “don't care”
after loading the instruction.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical "0" indicates that program-
ming is still in progress. DO at logical "1" indicates that
the register at the specified address has been erased
and the device is ready for another instruction. ERASE
instruction is valid if specified address is unprotected.
The ERASE cycle takes 4 ms per word typical.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
2.3
Data Protection
During power-up, all programming modes of operation
are inhibited until V
CC
has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V
CC
has fallen below 1.4V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
DS11181C-page 4
©
1995 Microchip Technology Inc.
93LCS56/66
6.0
WRITE
Note:
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. After the
last data bit is put on the DI pin, CS must be brought
low before the next rising edge of the CLK clock. This
falling edge of CS initiates the self-timed auto-erase
and programming cycle. The PE pin MUST be latched
“high” while loading the WRITE instruction but
becomes a “don't care” thereafter.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
(T
CSL
) and before the entire write cycle is complete.
DO at logical "0" indicates that programming is still in
progress. DO at logical "1" indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion. WRITE instruction is valid only if specified
address is unprotected.
The WRITE cycle takes 4 ms per word typical.
In order to execute either READ, EWEN,
ERAL, WRITE, WRAL, or EWDS instruc-
tions, the Protect Register Enable (PRE)
pin must be held LOW.
9.0
PROTECT REGISTER READ
The Protect Register Read (PRREAD) instruction out-
puts the address stored in the Protect Register on the
DO pin. The PRE pin MUST be held HIGH when load-
ing the instruction and remains HIGH until CS goes
LOW. A dummy zero bit precedes the 8-bit output
string. The output data bits in the memory Protect Reg-
ister will toggle on the rising edge of the CLK as in the
READ mode.
10.0
PROTECT REGISTER ENABLE
7.0
ERASE ALL
The ERAL instruction will erase the entire memory
array to the logical "1". The ERAL cycle is identical to
the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
at the falling edge of the CS. PE pin MUST be held
“high” while loading the instruction but becomes “don't
care” thereafter. Clocking of the CLK pin is not neces-
sary after the device has entered the self clocking
mode. The ERAL instruction is guaranteed at V
CC
=
4.5 to 6V and valid only when Protect Register is
cleared.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is com-
plete.
The ERAL cycle takes 15 ms maximum (8 ms typical).
The Protect Register Enable (PREN) instruction is
used to enable the PRCLEAR, PRWRITE, and PRDS
modes. Before the PREN mode can be entered, the
device must be in the EWEN mode. Both PRE and PE
pins MUST be held “high” while loading the instruction.
The PREN instruction MUST immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
11.0
PROTECT REGISTER CLEAR
The Protect Register Clear (PRCLEAR) instruction
clears the address stored in the Protect Register and,
therefore, enables all registers for programming
instructions such as ERASE, ERAL, WRITE, and
WRAL. The PRE and PE pin MUST be held HIGH
when loading the instruction. Thereafter, PRE and PE
pins become “don't care”. A PREN instruction must
immediately precede a PRCLEAR instruction.
12.0
PROTECT REGISTER WRITE
8.0
WRITE ALL
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. PE pin MUST be held
“high” while loading the instruction but becomes “don't
care” thereafter. Clocking of the CLK pin is not neces-
sary after the device has entered the self clocking
mode. The WRAL command does include an auto-
matic ERAL cycle for the device. Therefore, the WRAL
instruction does not require an ERAL instruction but the
chip must be in the EWEN status. The WRAL instruc-
tion is guaranteed at V
CC
= 4.5 to 6V and valid only
when Protect Register is cleared.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
The WRAL cycle takes 30 ms maximum (16 ms typi-
cal).
The Protect Register Write (PRWRITE) instruction
writes into the Protect Register the address of the first
register to be protected. After this instruction is exe-
cuted, all registers whose memory addresses are
greater than or equal to the address pointer specified in
the Protect register are protected from any program-
ming instructions. Note that a PREN instruction must
be executed before a PRWRITE instruction and, the
Protect Register must be cleared (by a PRCLEAR
instruction) before executing the PRWRITE instruction.
The PRE and PE pins MUST be held HIGH while load-
ing PRWRITE instruction. After the instruction is
loaded, they become “don't care”.
13.0
PROTECT REGISTER DISABLE
The Protect Register Disable (PRDS) instruction is a
ONE TIME ONLY instruction to permanently set the
address specified in the Protect Register. Any attempts
to change the address pointer will be aborted. The
PRE and PE pins MUST be held HIGH while loading
PRDS instruction. After the instruction is loaded, they
become “don't care”. Note that a PREN instruction
must be executed before a PRDS instruction.
©
1995 Microchip Technology Inc.
DS11181C-page 5
ADI Reference Circuit
京公网安备 11010802033920号
EEWORLD
