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JD54F20BDA

Description
Gate
Categorylogic    logic   
File Size140KB,6 Pages
Manufacturere2v technologies
Download Datasheet Parametric Compare View All

JD54F20BDA Overview

Gate

JD54F20BDA Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codecompliant
Base Number Matches1
54F 74F20 Dual 4-Input NAND Gate
November 1994
54F 74F20
Dual 4-Input NAND Gate
General Description
This device contains two independent gates each of which
performs the logic NAND function
Commercial
74F20PC
Military
Package
Number
N14A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F20DM (Note 2)
74F20SC (Note 1)
74F20SJ (Note 1)
54F20FM (Note 2)
54F20LM (Note 2)
J14A
M14A
M14D
W14B
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbol
IEEE IEC
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9462 – 2
TL F 9462 – 1
TL F 9462–3
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
b
1 mA 20 mA
A
n
B
n
C
n
D
n
O
n
Inputs
Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9462
RRD-B30M75 Printed in U S A

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