is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
18
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
Functional Description
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
GND
I/O
2
I/O3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
GND
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512K x 8
ARRAY
I/O
3
I/O
4
I/O
5
1049–2
CE
WE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
OE
1049–1
Selection Guide
7C1049-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l
Com’l
Ind’l
Military
Shaded areas contain advance information.
7C1049-15
15
220
8
0.5
9
7C1049-17
17
195
8
0.5
9
7C1049-20
20
185
8
0.5
9
10
7C1049-25
25
180
8
0.5
9
10
12
240
8
L
0.5
9
Cypress Semiconductor Corporation
Document #: 38-05063 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 31, 2001
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) .........................................20 mA
CY7C1049
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
V
CC
4.5V–5.5V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Test Conditions
7C1049-12
Min.
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l
Com’l
Ind’l
Military
Shaded areas contain advance information.
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
7C1049-15
Min.
2.4
Max.
0.4
2.2
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
220
40
7C1049-17
Min.
2.4
0.4
2.2
–0.3
–1
–1
V
CC
+ 0.3
0.3
+1
+1
195
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Max.
0.4
2.4
2.2
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
240
40
V
CC
= Min., I
OL
= 8.0 mA
I
SB2
8
L
0.5
9
10
8
0.5
9
10
8
0.5
9
10
mA
mA
mA
mA
Document #: 38-05063 Rev. **
Page 2 of 10
PRELIMINARY
Electrical Characteristics
Over the Operating Range (continued)
Test Conditions
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l
Com’l
Ind’l
Military
L
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–1
–1
7C1049-20
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
185
40
2.2
–0.3
–1
–1
Max.
CY7C1049
7C1049-25
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+1
180
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
0.5
9
10
8
0.5
9
10
mA
mA
mA
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255
Ω
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
Ω
GND
R1 481
Ω
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
≤
3ns
≤
3 ns
1049–3
1049–4
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
1.73V
OUTPUT
Document #: 38-05063 Rev. **
Page 3 of 10
PRELIMINARY
Switching Characteristics
[4]
Over the Operating Range
7C1049-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
12
10
10
0
0
10
7
0
3
6
0
12
15
12
12
0
0
12
8
0
3
7
3
6
0
15
17
12
12
0
0
12
8
0
3
0
6
3
7
0
3
12
6
0
7
3
12
12
3
15
7
0
15
15
3
17
Description
Min.
Max.
7C1049-15
Min.
Max.
CY7C1049
7C1049-17
Min.
Max.
Unit
ns
17
17
8
7
7
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
WRITE CYCLE
[7,8]
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
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