Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
55
53
68
66
10
27
23
29
*θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is specified for
device in socket for cerdip and P-DIP packages;
θ
JA
is specified for device
soldered to printed circuit board for SOL and PLCC packages.
CAUTION
1. Do not apply voltages higher than V
DD
+0.3 V or less than
–0.3 V potential on any terminal except V
REF
and R
FB
.
2. The digital control inputs are diode-protected; however,
permanent damage may occur on unconnected inputs from
high energy electrostatic fields. Keep in conductive foam at
all times until ready to use.
3. Use proper antistatic handling procedures.
4. Absolute Maximum Ratings apply to both packaged devices
and DICE. Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the device.
REV. A
–3–
DAC8408
Burn-in Circuit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8408 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
DICE CHARACTERISTICS
1. V
DD
2. V
REF
A
3. R
FB
A
4. I
OUT 1A
5. I
OUT 2A
/I
OUT 2B
6. I
OUT 1B
7. R
FB
B
8. V
REF
B
9. DB0 (LSB)
10. DB1
11. DB2
12. DB3
13. DB4
14. DB5
15. DB6
16. DB7 (MSB)
17. A/B
18. R/W
19.
DS1
20.
DS2
21. V
REF
D
22. R
FB
D
23. I
OUT 1D
24. I
OUT 2C
/I
OUT 2D
25. I
OUT 1C
26. R
FB
C
27. V
REF
C
28. DGND
DIE SIZE 0.130
×
0.124 inch, 16,120 sq. mils
(3.30
×
3.15 mm, 10.4 sq. mm)
–4–
REV. A
DAC8408
DAC A, B, C, & D.
WAFER TEST LIMITS
at V
Parameter
STATIC ACCURACY
Resolution
Nonlinearity
1
Differential Nonlinearity
Gain Error
Power Supply Rejection
(∆V
DD
=
±
10%)
2
I
OUT 1A, B, C, D
Leakage Current
DD
= +5 V; V
REF
=
10 V; V
OUT
A, B, C, D = 0 V; T
A
= +25 C, unless otherwise noted. Specifications apply for
Symbol
N
INL
DNL
G
FSE
PSR
I
LKG
V
REF
= +10 V
R
IN
R
IN
V
IL
V
IH
I
IN
V
OL
V
OH
I
LKG
I
DD
I
DD
Conditions
DAC8408G
Limits
8
±
1/2
±
1
±
1
0.001
±
30
Units
Bits min
LSB max
LSB max
LSB max
%FSR/% max
nA max
Using Internal R
FB
Using Internal R
FB
All Digital Inputs = 0 V
REFERENCE INPUT
Reference Input
Resistance
3
Input Resistance Match
DIGITAL INPUTS
Digital Input Low
Digital Input High
Input Current
4
DATA BUS OUTPUTS
Digital Output Low
Digital Output High
Output Leakage Current
POWER SUPPLY
Supply Current
5
Supply Current
6
6/14
±
1
0.8
2.4
±
1.0
1.6 mA Sink
400
µA
Source
0.4
4
±
1.0
50
1.0
kΩ min/max
% max
V max
V min
µA
max
V max
V min
µA
max
µA
max
mA max
NOTES
1
This is an endpoint linearity specification.
2
FSR is Full Scale Range = V
REF
–1 LSB.
3
Input Resistance Temperature Coefficient approximately equals +300 ppm/
°C.
4
Logic inputs are MOS gates.Typical input current at +25°C is less than 10 nA.
5
All Digital Inputs are either “0” or V
DD
.
6
All Digital Inputs are either V
IH
or V
IL
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
The golang language is also a framework language in the crawler. Of course, many web crawler novices will face the choice of what language is suitable for the crawler. Generally, many crawler users wi...
Live Topic: Power Integrity Design of Ideal Power Distribution Network
Live broadcast content:
Engineers know that the margins for power integrity designs are rapidly decreasing in low-power IoT devic...
High-brightness LEDs are specially processed PN junction semiconductor devices that can emit white, red, green or blue light (and may also produce other colors of light) when forward biased. As PN jun...