K7P323688M
K7P321888M
1Mx36 & 2Mx18 SRAM
32Mb M-die LW SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Dec. 2005
Rev 1.3
K7P323688M
K7P321888M
Document Title
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
1Mx36 & 2Mx18 SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 0.1
History
- Initial Document
- Recommended DC operating conditions are changed
Max V
DIF-CLK
: V
DDQ
+0.3 -> V
DDQ
+0.6
- AC Characteristics are changed
T
AVKH
/ T
DVKH
/ T
WVKH
/ T
SVKH
: 0.4 / 0.4 / 0.4 - > 0.3 / 0.3 / 0.3
T
KHAX
/ T
KHDX
/ T
KHWX
/ T
KHSX
: 0.5 / 0.6 / 0.7 - > 0.5 / 0.5 / 0.5
T
KHAX
/ T
KHDX
/ T
KHWX
/ T
KHSX
: 1.6 / 1.7 / 2.0 - > 1.5 / 1.6 / 2.0
Draft Date
Apr. 2002
Feb. 2003
Remark
Advance
Advance
Rev. 0.2
- PACKAGE PIN CONFIGURATION are changed
Numbering each SA pins.
- AC Characteristics are changed
T
KHQV (-33)
: 0.5 - > 0.6
- PIN CAPACITANCE is changed
Add Clock Pin capacitance
- Fill the themal Data
- Remove 333MHz Bin
- JTAG DC operating conditions are changed
Change VIH, VIL VOH, VOL
- Add Pb free.
- Modify package dimensions
Feb. 2003
Advance
Rev. 0.3
Mar. 2003
Advance
Rev. 0.4
May 2003
Advance
Rev. 1.0
Sep. 2004
Final
Rev. 1.1
Oct. 2004
Final
Rev. 1.2
Rev. 1.3
Oct. 2005
Dec. 2005
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-2-
Dec. 2005
Rev 1.3
K7P323688M
K7P321888M
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
FEATURES
• 1Mx36 or 2Mx18 Organizations.
• 1.8V V
DD
/1.5V or 1.8V V
DDQ
.
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1).
• 119(7x17) Flip Chip Ball Grid Array Package(14mmx22mm).
Org.
1Mx36
2Mx18
1Mx36 & 2Mx18 SRAM
Part Number
K7P323688M-H(G)C30
K7P323688M-H(G)C25
K7P321888M-H(G)C30
K7P321888M-H(G)C25
Maximum
Frequency
300MHz
250MHz
300MHz
250MHz
Access
Time
1.7
2.0
1.7
2.0
* G : Lead free package
FUNCTIONAL BLOCK DIAGRAM
SA[0:19]
or [0:20]
K,K
Clock
Buffer
Write
Address
Register
20 or 21
Read
Address
Register
20 or 21
2:1
MUX
Dec.
Data Out
36 or 18
S/A Array
36 or 18
MUX0
36 or 18
WAY
SS
SW
ZZ
G
Internal
Clock
Generator
OE
36 or 18
Control
Register
Control
Logic
E
Data Out
Register
36 or 18
36 or 18
XDIN
Data In
Register
(2 stage)
36 or 18
36 or 18
Memory Array
1Mx36
2Mx18
Data In
36 or 18
W/D
Array
DQ
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SS
SW
SWa
SWb
SWc
SWd
M
1
, M
2
G
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Select
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Read Protocol Mode Pins (M
1
=V
SS
, M
2
=V
DDQ
)
Asynchronous Output Enable
Pin Name
ZZ
ZQ
TCK
TMS
TDI
TDO
V
REF
V
DD
V
DDQ
V
SS
NC
Pin Description
Asynchronous Power Down
Output Driver Impedance Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
Dec. 2005
Rev 1.3
-3-
K7P323688M
K7P321888M
FUNCTION DESCRIPTION
1Mx36 & 2Mx18 SRAM
The K7P323688M and K7P321888M are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of
36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising
edge of K clock, all Addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated
from output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after
addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is
read between first rising and falling edges of K clock. Data outputs are updated from output registers off the falling edge of K clock.
During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write Operation(Late Write)
During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the
following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and
only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the
timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to
byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass
read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM arry.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-
tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
Mode Control
There are two mode control select pins (M
1
and M
2
) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M
1
must be connected to V
SS
and M
2
must be connected to V
DDQ
. These
mode pins must be set at power-up and must not change during device operation.
Programmable Impedance Output Driver
The data output driver impedance is adjusted by an external resistor, RQ, connected between ZQ pin and V
SS
, and is equal to RQ/5.
For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by test(10% by design)
and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that
do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance
updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Imped-
ance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and
proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles
have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up
requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-
read cycles. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to V
SS
or V
DDQ
.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
-5-
Dec. 2005
Rev 1.3
MCU
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