UPD46185084BF1-E40Y-EQ1-A datasheet, PDF

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UPD46185084BF1-E40Y-EQ1-A: DescriptionQDR SRAM; Categorystorage storage; File Size592KB，39 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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UPD46185084BF1-E40Y-EQ1-A Overview

QDR SRAM

UPD46185084BF1-E40Y-EQ1-A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	1277419775
package instruction	BGA-165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Samacsys Description	QDRII/DDRII/ QDRII+/DDRII+ SRAM
Samacsys Manufacturer	Renesas Electronics
Samacsys Modified On	2023-10-24 19:30:29
YTEOL	0
Maximum access time	0.45 ns
JESD-30 code	R-PBGA-B165
JESD-609 code	e6
length	15 mm
memory density	16777216 bit
Memory IC Type	QDR SRAM
memory width	8
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX8
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Maximum seat height	1.46 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN BISMUTH
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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Datasheet

PD46185084B

PD46185094B

PD46185184B

PD46185364B

18M-BIT QDR II SRAM

4-WORD BURST OPERATION

Description

The

PD46185084B is a 2,097,152-word by 8-bit, the

PD46185094B is a 2,097,152-word by 9-bit, the

PD46185184B is a 1,048,576-word by 18-bit and the

PD46185364B is a 524,288-word by 36-bit synchronous

quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory

cell.

The

PD46185084B,

PD46185094B,

PD46185184B and

PD46185364B integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are

latched on the positive edge of K and K#. These products are suitable for application which require

synchronous operation, high speed, low voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

R10DS0113EJ0200

Rev.2.00

Nov 09, 2012

Features

•

1.8 ± 0.1 V power supply

•

165-pin PLASTIC BGA (13 x 15)

•

HSTL interface

•

PLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports with concurrent transactions

•

100% bus utilization DDR READ and WRITE operation

•

Four-tick burst for reduced address frequency

•

Two input clocks (K and K#) for precise DDR timing at clock rising edges only

•

Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability. Normal operation is restored in 20

s after clock is resumed.

•

User programmable impedance output (35 to 70

Ω)

•

Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)

•

Simple control logic for easy depth expansion

•

JTAG 1149.1 compatible test access port

R10DS0113EJ0200 Rev.2.00

Nov 09, 2012

Page 1 of 38

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