OneNAND256
FLASH MEMORY
OneNAND SPECIFICATION
Product
OneNAND256
Part No.
KFG5616Q1M-DEB
KFG5616D1M-DEB
KFG5616U1M-DIB
V
CC
(core & IO)
1.8V(1.7V~1.95V)
2.65V(2.4V~2.9V)
3.3V(2.7V~3.6V)
Temperature
Extended
Extended
Industrial
PKG
63FBGA(LF)/48TSOP1
63FBGA(LF)/48TSOP1
63FBGA(LF)/48TSOP1
Version: Ver. 1.2
Date: June 15th, 2005
1
OneNAND256
FLASH MEMORY
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
OneNAND
™
‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their
rightful owners.
Copyright
©
2005, Samsung Electronics Company, Ltd
2
OneNAND256
Document Title
OneNAND
FLASH MEMORY
Revision History
Revision No. History
0.0
0.5
Initial issue.
1. Modified to preliminary specification.
2. Add the cache read operation and DQ toggling scheme.
1. Corrected the errata
2. ECC description is revised.
3. Changed Read while Load and Write While Program diagram.
4. Revised OTP Flow Chart
5. Added Multi Block Erase operation cases
6. Added Spare Assignment information
7. Added NAND Array Memory Map
8. Added OTP load/program/lock operation description
9. Revised OTP load/program/lock flow chart ; Excluded the fail case
10. Added Spare Assignment information
11. Added OTP Erase Fail case in Controller Status register output table
12. Added DC/AC parameters
13. Revised OTP area assignment
14. Added INT guidance
15. 2.65V device is added.
1. Corrected the errata
2. Changed Manufacturer ID from 0001h to 00ECh
3. Deleted BootRAM unlock/lock command
4. Revised 1.8V/2.65V/3.3V DC parameters
5. Revised tCES from 9ns to 7ns
6. Write Protection status register description is revised
1. Corrected the errata
2. Moved Interrupt register setting before inputting command in all flow
charts
3. Revised Dual operation diagrams
4. Added and revised the asynchronous read operation timing diagram
5. Revised the asynchronous write operation timing diagram
6. Added the tREADY parameter in Hot Reset operation
7. Revised typical tRD2 from 75us to 50us
8. Revised max tRD2 from 100us to 75us
9. Revised Write Protection status description
1. Revised Cold Reset and Warm Reset diagram
2. Added TSOP1 Package Information
3. Revised typical tOTP, tLOCK from 300us to 600us
4. Revised max tOTP, tLOCK from 600us to 1000us
5. Deleted Lock/Lock-tight All Block Operation
6. Added Endurance and Data Retention
Deleted Confidential Mark
Draft Date
Jan. 6, 2004
Mar. 24, 2004
Remark
Advance
Preliminary
0.6
May. 7, 2004
Preliminary
0.7
July. 6, 2004
Preliminary
0.8
August. 6, 2004
Preliminary
1.0
October. 21, 2004
Final
1.1
December. 17, 2004 Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
3
OneNAND256
Document Title
OneNAND
FLASH MEMORY
Revision History
Revision No. History
1.2
1. Added Copyright Notice in the beginning
2. Corrected Errata
3. Updated Icc2, Icc4, Icc5, Icc6 and I
SB
4. Revised INT pin description
5. Added OTP erase case NOTE
6. Revised case definitions of Interrupt Status Register
7. Added a NOTE to Command register
8. Added ECClogSector Information table
9. Removed ’data unit based data handling’ from description of Device
Operation
10. Revised description on Warm/Hot/NAND Flash Core Reset
11. Revised Warm Reset Timing
12. Added note for OTP
L
in Internal Register Reset
13. Removed all block lock default case after cold or warm reset
14. Added explanation for each prohibited case in protect mode
15. Revised the case of writing other commands during Multi Block Erase
routine
16. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode
17. Revised OTP operation description
18. Added supplemental explanation for ECC Operation
19. Removed classification of ECC error from ECC Operation
20. Removed redundant sentance from ECC Bypass Operation
21. Added technical note for Boot Sequence
22. Added technical note for INT pin connection guide
23. Excluded tOEH from Asynchronous Read Table
24. Revised Asycnchronous Read timing diagram for CE don’t care mode
25. Revised Asynchronous Write timing diagram for CE don’t care mode
26. Revised Load operation timing diagram for CE don’t care mode
Draft Date
Jun. 15, 2005
Remark
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
4
OneNAND256
1. FEATURES
•
Design Technology: 0.12µm
•
Voltage Supply
- 1.8V device(KFG5616Q1M) : 1.7V~1.95V
- 2.65V device(KFG5616D1M) : 2.4V~2.9V
- 3.3V device(KFG5616U1M) : 2.7V~3.6V
•
Organization
- Host Interface:16bit
•
Internal BufferRAM(3K Bytes)
- 1KB for BootRAM, 2KB for DataRAM
•
NAND Array
- Page Size : (1K+32)bytes
- Block Size : (64K+2K)bytes
FLASH MEMORY
♦
Architecture
♦
Performance
•
Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz
: Linear Burst - 4 , 8 , 16 , 32 words with wrap-around
: Continuous Sequential Burst(512 words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
•
Programmable Read latency
•
Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 2 sectors)
•
Multiple Reset
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
•
Power dissipation (typical values, C
L
=30pF)
- Standby current : 10uA@1.8V device, 15uA@2.65V/3.3V device
- Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 20mA@2.65V/3.3V device
- Load current : 20mA@1.8V device, 20mA@2.65V/3.3V device
- Program current: 20mA@1.8V device, 20mA@2.65V/3.3V device
- Erase current: 15mA@1.8V device, 18mA@2.65V/3.3V device
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
♦
Hardware Features
•
Voltage detector generating internal reset signal from Vcc
•
Hardware reset input (RP)
•
Data Protection
- Write Protection mode for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
•
User-controlled One Time Programmable(OTP) area
•
Internal 2bit EDC / 1bit ECC
•
Internal Bootloader supports Booting Solution in system
♦
Software Features
•
Handshaking Feature
- INT pin: Indicates Ready / Busy of OneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND
•
Detailed chip information by ID register
♦
Packaging
•
Package
- 63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA
- 48 TSOP 1, 12mm x 20mm, 0.5mm pitch
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