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9250BF-28LF-T

Description
Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size226KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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9250BF-28LF-T Overview

Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56

9250BF-28LF-T Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instruction0.300 INCH, GREEN, SSOP-56
Contacts56
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresALSO REQUIRES 2.5V SUPPLY
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length18.415 mm
Number of terminals56
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency133.32 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Master clock/crystal nominal frequency14.138 MHz
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.493 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS9250-28
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E and 815 type chipset.
Output Features:
2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
2 PCI (3.3 V) @33.3MHz
1 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
2
C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
2
C
control.
Pin Configuration
IOAPIC
VDDL
GND
*FS1/REF0
VDDREF
X1
X2
GND
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
FS0
GND
VDDA
PD#
SCLK
SDATA
GND
VDD48
48MHz_0
48MHz_1
FS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
Functionality
Block Diagram
FS2
0
0
REF0
PLL1
Spread
Spectrum
/2
/3
2
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
ICS9250-28
Function
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 133MHz
Active CPU = 133MHz
SDRAM = 100MHz
X1
X2
XTAL
OSC
1
1
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
1
1
FS(2:0)
PD#
Control
Logic
Config
Reg
/2
/2
3
13
2
SDATA
SCLK
PLL2
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
2
48MHz (1:0)
9250-28 Rev B 10/26/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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Description Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56 Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, SSOP-56 Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56 Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, SSOP-56 Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, SSOP-56
Is it Rohs certified? conform to incompatible conform to incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SSOP SSOP SSOP SSOP SSOP
package instruction 0.300 INCH, GREEN, SSOP-56 0.300 INCH, SSOP-56 0.300 INCH, GREEN, SSOP-56 SSOP, 0.300 INCH, SSOP-56
Contacts 56 56 56 56 56
Reach Compliance Code compliant not_compliant compliant compliant not_compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
Other features ALSO REQUIRES 2.5V SUPPLY ALSO REQUIRES 2.5V SUPPLY ALSO REQUIRES 2.5V SUPPLY ALSO REQUIRES 2.5V SUPPLY ALSO REQUIRES 2.5V SUPPLY
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609 code e3 e0 e3 e0 e0
length 18.415 mm 18.415 mm 18.415 mm 18.415 mm 18.415 mm
Number of terminals 56 56 56 56 56
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C
Maximum output clock frequency 133.32 MHz 133.32 MHz 133.32 MHz 133.32 MHz 133.32 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP SSOP SSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Master clock/crystal nominal frequency 14.138 MHz 14.138 MHz 14.138 MHz 14.138 MHz 14.138 MHz
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 2.794 mm 2.794 mm 2.794 mm 2.794 mm 2.794 mm
Maximum supply voltage 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface MATTE TIN Tin/Lead (Sn85Pb15) MATTE TIN TIN LEAD Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
width 7.493 mm 7.493 mm 7.493 mm 7.493 mm 7.493 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches 1 1 1 1 1
Peak Reflow Temperature (Celsius) 260 225 260 225 -
Maximum time at peak reflow temperature 30 20 30 30 -
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