Integrated
Circuit
Systems, Inc.
ICS9250-28
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E and 815 type chipset.
Output Features:
•
2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
•
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
•
2 PCI (3.3 V) @33.3MHz
•
1 IOAPIC (2.5V) @ 33.3 MHz
•
3 Hublink clocks (3.3 V) @ 66.6 MHz
•
2 (3.3V) @ 48 MHz (Non spread spectrum)
•
1 REF (3.3V) @ 14.318 MHz
Features:
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
•
I
2
C support for power management
•
Efficient power management scheme through PD#
•
Uses external 14.138 MHz crystal
•
Alternate frequency selections available through I
2
C
control.
Pin Configuration
IOAPIC
VDDL
GND
*FS1/REF0
VDDREF
X1
X2
GND
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
FS0
GND
VDDA
PD#
SCLK
SDATA
GND
VDD48
48MHz_0
48MHz_1
FS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
Functionality
Block Diagram
FS2
0
0
REF0
PLL1
Spread
Spectrum
/2
/3
2
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
ICS9250-28
Function
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 133MHz
Active CPU = 133MHz
SDRAM = 100MHz
X1
X2
XTAL
OSC
1
1
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
1
1
FS(2:0)
PD#
Control
Logic
Config
Reg
/2
/2
3
13
2
SDATA
SCLK
PLL2
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
2
48MHz (1:0)
9250-28 Rev B 10/26/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9250-28
General Description
The
ICS9250-28
is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the
ICS9112-17, the
ICS9250-28
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
Pin Configuration
PIN NUMBER
1
2, 56
4
P I N NA M E
IOAPIC
VDDL
FS1
REF0
TYPE
OUT
PWR
IN
OUT
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
IN
I/O
OUT
OUT
OUT
DESCRIPTION
2.5V clock output running at 33.3MHz.
2.5V power supply for CPU & IOAPIC
Function Select pin. Determines CPU frequency, all output functionality
3.3V, 14.318MHz reference clock output.
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Ground pins for 3.3V supply
3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
3.3V PCI clock outputs
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
Clock pin of I
2
C circuitry 5V tolerant
Data pin for I
2
C circuitry 5V tolerant
3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s .
3.3V output running 100MHz. All SDRAM outputs can be turned off
t h r o u g h I
2
C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS (2:0) pins.
5, 9, 14, 20, 25,
VDD
31, 35, 40, 44, 49
6
7
3, 8, 13, 17, 19,
24, 30, 34, 39,
43, 48, 52, 55
12, 11, 10
28, 18
16, 15
21
22
23
26, 27
X1
X2
GND
3V66 (2:0)
FS (2, 0)
PCICLK[1:0]
PD#
SCLK
SDATA
48MHz_0
29, 32, 33, 36,
SD
37, 38, 41, 42, (12RAM
:0)
45, 46, 47, 50, 51
54, 53
CPUCLK (1:0)
2
ICS9250-28
Power Down Waveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2.
Power-up latency <3ms.
3.
Waveform shown for 100MHz
Maximum Allowed Current
815
Condition
Powerdown Mode
(PWRDWN# = 0
Full Active 66MHz
FS[2:0] = 010
Full Active 100MHz
FS[2:0] = 011
Full Active 133MHz
FS[2:0] = 111
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
10mA
70mA
100mA
130mA
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
10mA
400mA
400mA
450mA
Clock Enable Configuration
PD#
0
1
CPUCLK
LOW
ON
SDRAM
LOW
ON
IOAPIC
LOW
ON
66MHz
LOW
ON
PCICLK
LOW
ON
REF,
48MHz
LOW
ON
Osc
OFF
ON
VCOs
OFF
ON
3
ICS9250-28
Truth Table
FS2
0
0
1
1
1
1
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
CPU
Tristate
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
Tristate
TCLK/3
66.6 MHz
66.6 MHz
66.6 MHz
66.6 MHz
PCI
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
Tristate
TCLK
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
IOAPIC
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
Undefined bit (Note 3)
Undefined bit (Note 3)
Bit 0
0
0
0
Bit 0
0
1
1
1
1
FS0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
Desctiption
PWD
0
0
0
0
0
X
X
CPUCLK SDRAM
MHz
MHz
66.66
100.0
133.32
133.32
66.66
100.0
133.32
133.32
100.0
100.0
133.32
100.0
100.0
100.0
133.32
133.32
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
PCICLK IOAPIC
MHz
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0
Note 1
Note 1:
For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3:
Undefined bits can be written either as "1 or 0"
4
ICS9250-28
Byte 0: Control Register
(1 = enable, 0 = disable)
Name
PWD
Reserved ID
0
Reserved ID
0
Reserved ID
0
Reserved ID
1
SpreadSpectrum
Bit 3
-
1
(1=On/0=Off)
Bit 2
27
48MHz 1
1
Bit 1
26
48MHz 0
1
Bit 0
-
Reserved ID
0
Note: Reserved ID bits must be written as "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Pin#
-
-
-
-
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
38
41
42
45
46
47
50
51
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
PWD
1
1
1
1
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
12
29
32
33
36
37
16
-
Name
3V66-2 (AGP)
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
PCICLK1
Reserved
PWD
1
1
1
1
1
1
1
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
5
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