CXD2500BQ
CD Digital Signal Processor
Description
The CXD2500BQ is a digital signal processing LSI
designed for use in compact disc players. It has the
following functions:
•
Wide-frame jitter margin (±28 frames) realized by a
built-in 32K RAM.
•
Bit clock generated by digital PLL for strobing EFM
signals. Capture range of ±150 kHz and over.
•
EFM data demodulation
•
Enhanced protection of EFM Frame Sync signals
•
Powerful error correction based on Refined Super
Strategy
C1: Double correction
C2: Quadruple correction
•
Double-speed playback and vari-pitch playback
•
Reduced noise generation at track jump
•
Auto zero-cross muting
•
Subcode demodulation and subcode Q data error
detection
•
Digital spindle servo system (incorporating an
oversampling filter)
•
16-bit traverse counter
•
Built-in asymmetry correction circuit
•
CPU interface using a serial bus
•
Servo auto sequencer
•
Output for digital audio interface
•
Built-in digital level meter and peak meter
•
Bilingual
Features
•
All digital signals for regeneration are processed
using one chip.
•
The built-in RAM enables high-integration
mounting.
Structure
Silicon-gate CMOS IC
Error correction
80 pin QFP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E91Y46F64-TE
CXD2500BQ
Absolute Maximum Ratings
(Ta=25 °C)
•
Supply voltage
V
CC
•
Input voltage
V
I
•
Output voltage
V
O
•
Operating temperature
Topr
•
Storage temperature
Tstg
•
Supply voltage differences
V
SS
–AV
SS
V
DD
–AV
DD
Recommended Operating Conditions
•
Supply voltage
V
DD
•
Operating temperature
•
Input voltage
Topr
V
IN
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–20 to +75
–40 to +125
–0.3 to +0.3
–0.3 to +0.3
V
V
V
°C
°C
V
V
4.75
∗
1
to 5.25
∗
3
(5.0 V typ.)
–20 to +75
V
SS
–0.3 to + V
DD
+ 0.3
V
°C
V
∗
1
V
DD
value of 4.75 V (min.) is for the double-speed playback mode at vari-pitch control reset. For the low
power consumption special playback mode, V
DD
value is 3.6 V (min.).
∗
2
In the normal-speed playback
mode V
DD
value is 4.5 V (min.)
∗
2
Low power consumption, special playback mode
Set the internal operation of LSI at the double-speed mode, and half the crystal oscillation frequency. This
will result in the normal-speed playback mode.
∗
3
V
DD
value of 5.25 V (max.) is for the double-speed playback mode at vari-pitch control reset. For normal-
speed playback and the low power consumption special playback mode, the V
DD
value is 5.5 V (max.).
I/O Capacity
•
Input pins
CI 12 pF max.
•
Output pins
CO 12 pF max. at high impedance
Note: Test Conditions
V
DD
=V
I
=0 V
f
M
=1 MHz
—2—
CXD2500BQ
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
FOK
FSW
MON
MDP
MDS
LOCK
NC
VCOO
VCOI
TEST
PDO
V
SS
NC
NC
NC
VPCO
VCKI
FILO
FILI
PCO
AV
SS
CLTV
AV
DD
RF
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK
LRCK
V
DD
DA16
DA15
DA14
DA13
DA12
DA11
DA10
O
I
O
I
O
I
I
I
I
O
I
I
O
O
O
O
O
—
O
I
I
O
—
—
—
Output of charge pump for vari-pitch PLL
Clock input from external VCO for vari-pitch control. fc
center
=16.9344 MHz.
Analog Output of filter for master PLL (Slave=Digital PLL)
Input to filter for master PLL
1, Z, 0 Output of charge pump for master PLL
Analog GND
VCO control voltage input for master PLL
Analog power supply (+5 V)
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparator circuit voltage input
1, 0
EFM full-swing output
Asymmetry circuit OFF at “L”. Asymmetry circuit ON at “H”.
—
Input used to switch the audio data output mode. “L” for serial output,
“H” for parallel output.
1, 0
D/A interface for 48-bit slot. Word clock f=2Fs
D/A interface for 48-bit slot. LR clock f=Fs
1, 0
Power supply (+5 V)
Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot
1, 0
(2’s complements, MSB first) when PSSL=0.
1, 0
Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0.
Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2’s
1, 0
complements, LSB first) when PSSL=0.
1, 0
Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0.
1, 0
Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0.
1, 0
1, 0
Outputs DA11 when PSSL=1, or GTOP when PSSL=0.
Outputs DA10 when PSSL=1, or XUGF when PSSL=0.
—5—
1, Z, 0
1, 0
Output of oscillation circuit for analog EFM PLL
Input to oscillation circuit for analog EFM PLL f
LOCK
=8.6436 MHz
Test. Normally at 0 V (GND).
Output of charge pump for analog EFM PLL
GND
I/O
Description
Focus OK input. Used for SENS output and servo auto sequencer.
Output used to switch the spindle motor output filter.
Output for spindle motor ON/OFF control
Output for spindle motor servo control
Output for spindle motor servo control
Output is “H” when the GFS signal sampled at 460 Hz is “H”. Output is
“L” when the GFS signal is “L” 8 or more times in succession.
Z, 0
1, 0
1, Z, 0
1, Z, 0
1, 0
1, Z, 0
I
O
O
O
O
O
O
O
O
O
MEMS sensors
京公网安备 11010802033920号
EEWORLD
