CXG1015N
Power Amplifier/Antenna Switch for PHS
Description
The CXG1015N is a power amplifier/antenna
switch MMIC for PHS. This is designed using the
Sony’s GaAs J-FET process and operates at a
single positive power supply.
Features
•
Single positive power supply
20 pin SSOP (Plastic)
3.0 V
•
Output power
20.2 dBm
(Antenna switch transfer output pin power)
•
Low current consumption
160 mA
(Output power of 20.2 dBm)
•
High power gain
•
Low insertion loss
•
Small mold package
39 dB Typ.
(Output power of 20.2 dBm)
0.5 dB Typ.
20-pin SSOP
(Pin interval of 0.5 mm pitch)
Structure
GaAs J-FET MMIC
Applications
•
Power amplifiers for PHS
•
Antenna switches for PHS
Absolute Maximum Ratings
(Ta=25 °C)
•
Supply voltage
V
DD
6
•
Voltage between gate and source
Vgs0
•
Drain current
I
DD
•
Power dissipation
•
Channel temperature
•
Operating temperature
•
Storage temperature
P
D
Tch
Topr
Tstg
1.5
550
V
V
mA
W
°C
°C
°C
3
150
–35 to +85
–65 to +150
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E97749-TE
CXG1015N
Electrical Characteristics
Power Amplifier + Antenna Switch Transfer Block
V
DD
=3.0 V, V
CTL
=2.0 V, f=1.90 GHz
Item
∗
Current consumption
∗
Gate voltage adjustment value
Output power
(Power Amplifier + Antenna Switch Transfer Block)
(Ta=25 °C)
Min.
0
20.2
35.5
39
–59
42
–54
Typ.
160
0.25
Max.
0.7
Unit
mA
V
dBm
dB
dBc
Symbol
I
DD
V
GG
2
P
OUT
G
P
ACPR600
∗
Power gain
∗
Adjacent channel leak power ratio
(600 kHz±100 kHz)
∗
Values where V
GG
1 and V
GG
2 are adjusted so that I
DD
becomes 160 mA when the power amplifier output
pin and the antenna switch transfer input pin are connected on the Sony’s recommended evaluation board
and the output power on the antenna switch transfer output pin is 20.2 dBm.
Antenna Switch Receive Block
V
CTL
(L)=0 V, V
CTL
(H)=3.0 V
Item
Insertion loss
Isolation
Control pin current
Symbol
IL
ISO
I
CTL
Min.
20
Typ.
0.5
24
40
Max.
0.8
100
(Ta=25 °C)
Unit
dB
dB
µA
—2—
CXG1015N
Block Diagram
V
DD
1
V
DD
2
V
DD
3
R
X
V
CTL
2
PA
IN
ANT
V
GG
1
VP
CTL
V
GG
2 PA
OUT
T
X
V
CTL
1
Pin Configuration
1
PA
IN
GND
V
DD
1
GND
V
DD
2
GND
V
DD
3
GND
R
X
V
CTL
2
20
V
GG
1
VP
CTL
GND
V
GG
2
GND
PA
OUT
GND
T
X
V
CTL
1
ANT
Antenna Switch Operation
V
CTL
1=3 V
V
CTL
2=0 V
V
CTL
1=0 V
V
CTL
2=3 V
ANT-T
X
ANT-R
X
ANT-T
X
ANT-R
X
ON
OFF
OFF
ON
Gate Bias Circuit of Power Amplifier Block
V
GG
2
Gate voltage
adjustment pin
1kΩ
V
GG
1
Recommended Current Adjustment Method
(1) V
GG
2/P
IN
separate adjustment
(V
GG
2 adjustment 1)
(P
IN
adjustment 1)
When the RF input
(P
IN
) off, the current
consumption (I
DD
) is
adjusted to 160 mA.
Variation of I
DD
and
P
OUT
due to adjustment
(2) Simple adjustment
(I
DD
read)
When the RF input (P
IN
)
is off, the gate voltage
(V
GG
2) is set to 0.4 V
and I
DD
is read.
The output power
(P
OUT
) is adjusted
to 20.2 dBm.
I
DD
=160±20 mA
P
OUT
=20.2 dBm
(V
GG
2 adjustment 2)
The current
consumption (I
DD
)
is finely adjusted to
160 mA.
I
DD
=160 mA
P
OUT
=20.2±0.2 dBm
(P
IN
adjustment 2)
The output power
(P
OUT
) is finely
adjusted to 20.2 dBm.
I
DD
=160±5 mA
P
OUT
=20.2 dBm
(V
GG
2 setting)
The formula
∗
where
V
GG
2=f (I
DD
: V
GG
2=0.4 V)
is used to set V
GG
2.
∗
e.g. V
GG
2=a-b
×
I
DD
(P
IN
adjustment)
The output power (P
OUT
)
is adjusted to 20.2 dBm.
I
DD
=160±5 mA
P
OUT
=20.2 dBm
—3—
CXG1015N
Recommended Evaluation Circuit
PA
IN
V
GG
2
R1=1kΩ
GND
L1=1.8nH
L2=2.2nH
L3=18nH
C1=1pF
C2=30pF
C3=100pF
C4=1nF
C5=10nF
V
DD
L2
L3
C4
C4
C5
C2
L3
C3
C1
L2
C2
C2
C3
C3
C2
R1
C4
VP
CTL
R
X
L1
GND
Via
Hole
V
CTL
2
V
CTL
1
ANT
Glass fabric-base epoxy board
GND for the overall back side
Dimension : 25 mm
×
25 mm
Thickness : 0.2 mm
Recommended Gate Bias Circuit and Circuit Characteristics
(V)
3.0V
V
GG
2
100Ω
6.8kΩ
R
V
1 Variable
resistor R
V
R
V
2 10kΩ (Max.)
180Ω
V
GG
2
0.5
1kΩ
0
5
R
V
1 (kΩ)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—4—
CXG1015N
Recommended External Circuit
2.2nH
PA
IN
1
2
1nF 18nH 1nF
20
100pF
(V
GG
1)
19
VP
CTL
V
DD
1
3
4
18
1kΩ
17
V
GG
2
1nF 18nH 30pF
V
DD
2
5
6
16
1pF 2.2nH
(PA
OUT
)
15
10nF 1.8nH
V
DD
3
7
8
14
30pF
13
100pF
V
CTL
1
30pF
(T
X
)
30pF
R
X
9
10
100pF
12
V
CTL
2
11
ANT
Example of Representative Characteristics
(Ta=25 °C)
Antenna Switch Receive Block
IL, Iso. vs. Freq.
0
IL
–1
–10
0
IL-Insertion loss (dB)
–2
–20
–3
Iso.
–30
–4
–40
–5
0
1
2
Frequency (GHz)
3
–50
—5—
Iso.-Isolation (dB)
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