54FCT573 Octal D-Type Latch with TRI-STATE Outputs
August 1998
54FCT573
Octal D-Type Latch with TRI-STATE
®
Outputs
General Description
The ’FCT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE) in-
puts.
This device is functionally identical to the ’FCT373 but has
different pinouts.
Features
n
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n
Useful as input or output port for microprocessors
n
TTL input and output level compatible
n
CMOS power consumption
n
Functionally identical to ’FCT373
n
TRI-STATE outputs for bus interfacing
n
Output sink capability of 32 mA, source capability of
12 mA
n
Standard Microcircuit Drawing (SMD) 5962-8863901
Ordering Code
Military
54FCT573DMQB
54FCT573FMQB
54FCT573LMQB
Package
Number
J20A
W20A
E20A
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
Connection Diagram
Pin Assignment
for DIP and Cerpack
Pin Assignment
for LCC
DS100951-39
DS100951-1
Pin
Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Description
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input
(Active LOW)
TRI-STATE Latch Outputs
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100951
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54FCT573
Functional Description
The ’FCT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
OE
L
L
L
H
H
H
L
X
Function Table
Inputs
LE
D
H
L
X
X
Outputs
O
H
L
O
0
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O
0
= Value stored from previous clock cycle
Logic Diagram
DS100951-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
54FCT573
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
−65˚C to +150˚C
−55˚C to +125˚C
−55˚C to +175˚C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
in LOW State (Max)
DC Latchup Source Current
Twice the rated I
OL
(mA)
−500 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Supply Voltage
Military
Minimum Input Edge Rate
Data Input
Enable Input
−55˚C to +125˚C
+4.5V to +5.5V
(∆V/∆t)
50 mV/ns
20 mV/ns
−0.5V to +5.5V
−0.5V to V
CC
Note 1:
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Quiescent Power Supply Current
Quiescent Power
Supply Current
Dynamic I
CC
54FCT
54FCT
V
OL
54FCT
54FCT
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CCQ
∆I
CC
I
CCD
4.3
2.4
0.2
0.5
5
−5
50
−50
-60
1.5
2.0
0.4
µA
µA
µA
µA
mA
mA
mA
mA/
MHz
Max
Max
0−
5.5V
0−
5.5V
Max
Max
Max
Max
V
Min
2.0
0.8
−1.2
FCT573
Typ
Max
V
V
V
V
Min
Min
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18 mA
I
OH
= −300 µA
I
OH
= −12 mA
I
OL
= 300 µA
I
OL
= 32 mA
V
IN
= V
CC
V
IN
= 0.0V
V
OUT
= 2.7V; OE = 2.0V
V
OUT
= 0.5V; OE = 2.0V
V
OUT
= 0.0V
V
IN
<
0.2V or V
IN
5.3V, V
CC
=
5.5V
V
I
= 3.4V, V
CC
= 5.5V
Outputs Open, V
CC
= 5.5V, V
IN
5.3V or V
IN
<
0.2V, One Bit
Toggling, 50% Duty Cycle, OE =
GND, LE = V
CC
Outputs Open, f
CP
= 10 MHz,
V
CC
= 5.5V, V
IN
5.3V or V
IN
<
0.2V, One Bit Toggling, 50%
Duty Cycle, OE = GND, LE =
V
CC
Units
V
CC
Conditions
I
CC
Total Power Supply
Current
6.0
mA
Max
3
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54FCT573
AC Electrical Characteristics
Symbol
Parameter
54FCT
T
A
= −55˚C to +125˚C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
8.5
8.5
15.0
15.0
13.5
13.5
10.0
10.0
ns
ns
ns
ns
Units
Fig.
No.
Figure 4
Figure 4
Figure 6
Figure 6
AC Operating Requirements
Symbol
Parameter
54FCT
T
A
= −55˚C to +125˚C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Set Time, HIGH
or LOW D
n
to LE
Hold Time, HIGH
or LOW D
n
to LE
Pulse Width,
LE HIGH
2.0
2.0
1.5
1.5
6.0
ns
ns
Max
ns
Units
Fig.
No.
Figure 7
Figure 7
Figure 5
Capacitance
Symbol
C
IN
C
OUT
(Note 3)
Parameter
Input Capacitance
Output Capacitance
Max
10
12
Units
pF
pF
Conditions
(T
A
= 25˚C)
V
CC
= 0V
V
CC
= 5.0V
Note 3:
C
OUT
is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012.
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54FCT573
AC Loading
DS100951-4
*Includes jig and probe capacitance
FIGURE 1. Test Load
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100951-5
DS100951-6
DS100951-7
FIGURE 2. Test Input Signal Levels
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
t
f
2.5 ns
Amplitude
3.0V
Rep. Rate
1 MHz
t
w
500 ns
t
r
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100951-9
DS100951-8
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
5
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