M
Features
•
•
•
•
•
•
TC1142
Package Type
8-Pin MSOP
V
OUT
1
C2– 2
C2+
3
8
CCLK
V
IN
C1+
GND
Inductorless -2x Boost/Buck Regulator
Input Range 2.5V to 5.5V
Regulated Output Options from -3.0 to -5.0V
Output Current 20mA (max)
200kHz Internal Oscillator Frequency
External Synchronizing Clock Input
Logic Level Shutdown
- 1µA (max) Supply Current
• Available in 8-Pin MSOP Package
TC1142
7
6
5
C1– 4
Applications
• Cellular Phones
• Battery Powered/Portable Equipment
General Description
The TC1142 generates a regulated negative voltage
from -3V to -5V at 20mA from an input of 2.5V to 5.5V,
using only three external capacitors. Other boost/buck
switching regulators must use an inductor, which is
larger and radiates EMI. An internal voltage
comparator inhibits the charge pump when V
OUT
is
more negative than the regulated value (per the
ordering option). The values of flying capacitors C1 and
C2 are chosen to be less than C
OUT
in order to reduce
the ripple generated from regulating V
OUT
in this
manner. The TC1142 also can be used as a -1x buck
regulator by omitting C2, and connecting the C2 pin to
V
OUT
.
The part goes into shutdown when the CCLK input is
driven low. When in shutdown mode, the part draws a
maximum of 1µA. When CCLK is pulled high, the part
runs from the internal 200kHz oscillator. The device
may be run with an external clock, provided the
frequency is greater than 3kHz and less than 500kHz.
The TC1142 comes in a space-saving MSOP package.
Device Selection Table
Part
Number
TC1142-3.0EUA
TC1142-4.0EUA
TC1142-5.0EUA
Output
Voltage
(V)*
3.0
4.0
5.0
Package
Operating
Temp.
Range
8-Pin MSOP -40°C to +85°C
8-Pin MSOP -40°C to +85°C
8-Pin MSOP -40°C to +85°C
*Other output voltages are available (-3.5V and -4.5V). Please
contact Microchip Technology Inc. for details.
Functional Block Diagram
+
–
ON OFF
V
IN
CCLK
V
OUT
4.7µF
C
OUT
OSC
OVERRIDE
0.47µF
C1
V
OUT
= -5.0V
5.5V to 2.5V
ON OFF
V
IN
CCLK
V
OUT
4.7µF
C
OUT
V
OUT
= –3.0V
–2x Boost/Buck
+
–
5.5V to 3V
–1x Buck
OSC
OVERRIDE
0.47µF
C1
TC1142-50
TC1142-30
C2–
0.47µF
C2
GND
GND
2002 Microchip Technology Inc.
DS21360B-page 1
TC1142
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (V
IN
) with C
OUT
Connected ..........6.5V
CCLK Voltage................................-0.3V to (V
+
+ 0.3V)
Power Dissipation.............................................320mW
Operating Temperature Range
8-Pin MSOP .................................-40°C to +85°C
Storage Temperature Range ..............-65°C to +160°C
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
TC1142 ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
R
L
=
∞
, V
IN
= 3.2V, Mode = -2x, C1 = C2 = 0.47
µ
F (Note 1), CCLK = V
IH
, C
OUT
= 4.7
µ
F, for V
R
= 3V,
V
IN
= 3.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Symbol
V
IN
V
OUT
V
P-P
I
SUPPLY
I
SUPPLY1
R
OUTCL
R
OUT
f
OSC
f
CCLK
P
EFF
V
IH
V
IL
Note
1:
2:
3:
4:
Parameter
Supply Voltage
Output Voltage
Output Ripple
Supply Current
Closed-Loop Output Resistance
Open-Loop Output Resistance
Internal Oscillator Frequency
External Clock Frequency, Typical
Power Efficiency
CCLK Input High Threshold
CCLK Input Low Threshold
Min
2.5
-(V
R
+ 0.2)
—
—
—
—
—
150
3
70
2.2
—
Typ
—
-V
R
100
200
0.1
2
30
200
—
76
—
—
Max
5.5
-(V
R
– 0.2)
—
400
1
6
—
275
500
—
—
1.0
Units
V
V
mV
µ
A
µ
A
Ω
Ω
Test Conditions
I
L
= 0mA (Note 2)
I
L
= 10mA
CCLK = 0V
(Note 3)
(Note 4)
I
L
= 10mA, V
R
= 5V; (See Equation 3-5)
kHz
kHz
%
V
V
Assume C1 and C2 have an ESR of 1
Ω.
V
R
is the voltage output specified in the ordering option.
Measured in -1x Mode. For V
R
= 3V, V
IN
= 2.5V.
CCLK is driven with an external clock. Minimum frequency = 1/2t
0
at 50% duty cycle, where t
0
is the counter timeout period.
DS21360B-page 2
2002 Microchip Technology Inc.
TC1142
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin No.
(8-Pin MSOP)
1
2
3
4
5
6
7
8
PIN FUNCTION TABLE
Symbol
V
OUT
C2–
C2+
C1–
GND
C1+
V
IN
CCLK
Regulated negative output voltage.
Negative terminal of flying capacitor C2.
Positive terminal of flying capacitor C2.
Negative terminal of flying capacitor C1.
Power supply ground.
Positive terminal of flying capacitor C1.
Power supply positive voltage input (2.5V to 5.5V).
Clock control input:
If low, the TC1142 is in Shutdown mode (1
µ
A, max).
If high, the TC1142 runs off the internal oscillator (200kHz, typ.).
CCLK can be overridden by an external oscillator from 3kHz to 500kHz.
Description
2002 Microchip Technology Inc.
DS21360B-page 3
TC1142
3.0
DETAILED DESCRIPTION
The TC1142 inductorless -2x boost/buck regulator is an
inverting charge pump that uses a pulse-frequency
modulation (PFM) control scheme to produce a
regulated negative output voltage, -V
R
, between -3V
and -5V (depending on the output voltage option) at
20mA maximum load. Output voltage regulation is
achieved by gating ON the clock to the charge pump for
a single half-clock period whenever the output is more
positive than V
R
, and gating it OFF when the output is
more negative than -V
R
. The resulting PFM of the clock
applied to the charge pump has a high frequency
spectral content consisting only of clock harmonics.
When using an external clock, the transient noise is
then synchronized to the clock and is easier to filter in
sensitive applications.
The TC1142 also can be used as a -1x boost/buck
regulator by omitting the C2 capacitor and connecting
the C2– pin to V
OUT
.
The PFM control scheme minimizes supply current at
small loads and permits the use of low value flying
capacitors, which saves on printed circuit board space
and cost. Due to the TC1142’s doubling and inverting
charge pump mechanism, the output voltage is limited
to -2V
IN
. To produce a -5V regulated output, for
example, a minimum input voltage of 2.5V is required
at V
IN
.
The CCLK pin of the TC1142 has three functions: It can
select the internal 200kHz oscillator (when held HIGH),
put the TC1142 into shutdown (when held LOW), or
provide an external clock input. To achieve this
functionality, an internal counter is reset by any positive
transition at the CCLK pin, but will time out in typically
160
µsec
(i.e., a frequency higher than about 3kHz). If
the counter times out following the last positive
transition, then the internal clock will be gated through
to the charge pump if CCLK is HIGH, or the device will
enter shutdown mode if it is LOW. To enter shutdown,
CCLK must be LOW and the counter must have timed
out. These timing diagrams are shown in Figure 3-4.
A functional circuit diagram of the TC1142 is shown in
Figure 3-1. The output voltage V
OUT
is compared to an
on-chip reference voltage, and the comparator output
is used to gate the charge pump clock. The charge
pump is a negative voltage doubler and has two
phases of operation which are further illustrated in
Figure 3-2 and Figure 3-3. In phase 1, shown in
Figure 3-2, the flying capacitor C1 charges the flying
capacitor C2 while the device load is totally serviced by
the charge stored on the reservoir capacitor C
OUT
. In
phase 2, shown in Figure 3-3, the capacitor C1 is
recharged to V
IN
while the capacitor C2 transfers its
charge to the reservoir capacitor C
OUT
.
In normal operation, the TC1142 charge pump stays in
phase 2 and only switches to phase 1 as required to
maintain output voltage regulation.
FIGURE 3-1:
FUNCTIONAL CIRCUIT DIAGRAM
C1+
V
IN
C1–
C2+
V
IN
V
OUT
C2–
+
Shutdown
Clock
Circuit
OSC
Override
+
–
1.2V
+
C
OUT
DS21360B-page 4
2002 Microchip Technology Inc.
TC1142
FIGURE 3-2:
TC1142 PHASE 1
(a)
C1+
V
IN
C1–
C2+
V
IN
V
OUT
C2–
+
C
OUT
(b)
V
IN
C2+
C1+
V
OUT
+
C
OUT
C1–
C2–
C1+
(a) Switch positions during phase 1.
(b) The equivalent circuit of the charging phase of operation.
FIGURE 3-3:
(a)
TC1142 PHASE 2
C1+
V
IN
C1–
C2+
V
IN
V
OUT
C2–
+
C
OUT
(b)
V
IN
C1+
C2–
C2+
C1–
+
C
OUT
V
OUT
(a) Switch positions during phase 2.
(b) The equivalent circuit of the discharging phase of operation.
2002 Microchip Technology Inc.
DS21360B-page 5
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