CY7C1346H-166AXI datasheet, PDF

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CY7C1346H-166AXI: Description2-mbit (64k x 36) pipelined sync sram; File Size682KB，16 Pages; ManufacturerCypress Semiconductor

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2-mbit (64k x 36) pipelined sync sram

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CY7C1346H

2-Mbit (64K x 36) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 64K × 36 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

— 3.5 ns (166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1346H SRAM integrates 64K x 36 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and CE

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1346H operates from a +3.3V core power supply

while all outputs also operate with either a +3.3V/2.5V supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

A0, A1, A

ADDRESS

[1:0]

MODE

ADV

CLK

ADSC

ADSP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

BURST

COUNTER

CLR

AND

LOGIC

,DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

DQP

BYTE

WRITE DRIVER

DQP

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

REGISTERS

OUTPUT

BUFFERS

DQs

DQP

BWE

ENABLE

PIPELINED

ENABLE

INPUT

REGISTERS

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05672 Rev. *B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised April 26, 2006

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	CY7C1346H-166AXI
Description	2-mbit (64k x 36) pipelined sync sram

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