CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Single-channel HOTLink II™ Transceiver
Features
• Second-generation HOTLink
®
technology
• Compliant to multiple standards
— ESCON
®
, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— CPRI™ compliant
— CYW15G0101DXB compliant to OBSAI-RP3
— CYV15G0101DXB compliant to SMPTE 259M and
SMPTE 292M
— 8B/10B encoded or 10-bit unencoded data
• Single-channel transceiver operates from 195 to
1500 MBaud serial data rate
— CYW15G0101DXB operates from 195 to 1540 MBaud
•
•
•
•
Selectable parity check/generate
Selectable input clocking options
Selectable output clocking options
MultiFrame™ Receive Framer
— Bit and Byte alignment
— Comma or full K28.5 detect
— Single- or Multi-Byte framer for byte alignment
•
•
•
•
— Low-latency option
Synchronous LVTTL parallel input and parallel output
interface
Internal phase-locked loops (PLLs) with no external
PLL components
Dual differential PECL-compatible serial inputs
— Internal DC-restoration
Dual differential PECL-compatible serial outputs
—
Source matched for driving 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Optional Elasticity Buffer in Receive Path
CYP(V)(W)15G0101DXB
• Optional Phase Align Buffer in Transmit Path
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
•
•
•
•
•
— Digital signal detect
Low power 1.25W @ 3.3V typical
Single 3.3V supply
100-ball BGA
Pb-Free package option available
0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0101DXB
[1]
single-channel HOTLink II™
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. The receive channel accepts serial data and
converts it to parallel data, frames the data to character bound-
aries, decodes the framed characters into data and special
characters, and presents these characters to an Output
Register.
Figure 1
illustrates typical connections between
independent
host
systems
and
corresponding
CYP(V)(W)15G0101DXB parts. As a second-generation
HOTLink device, the CYP(V)(W)15G0101DXB extends the
HOTLink II family with enhanced levels of integration and
faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices.
CYP(V)(W)15G0101DXB
System Host
10
10
10
10
Serial Link
Backplane or Cabled
Connections
Note:
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum
operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and
also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices.
Figure 1. HOTLink II System Connections
Cypress Semiconductor Corporation
Document #: 38-02031 Rev. *J
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 24, 2005
System Host
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
The CYW15G0101DXB
[1]
operates from 195 to 1540 MBaud,
which includes operation at the OBSAI RP3 datarate of both
1536 MBaud and 768 MBaud.
The CYV15G0101DXB satisfies the SMPTE 259M and
SMPTE 292M compliance as per the EG34-1999 Pathological
Test Requirements. The transmit (TX) section of the
CYP(V)(W)15G0101DXB single-channel HOTLink II consists
of a byte-wide channel. The channel can accept either eight-bit
data characters or pre-encoded 10-bit transmission
characters. Data characters are passed from the Transmit
Input Register to an embedded 8B/10B Encoder to improve
their serial transmission characteristics. These encoded
characters are then serialized and output from dual Positive
ECL (PECL)-compatible differential transmission-line drivers
at a bit-rate of either 10 or 20 times the input reference clock.
The receive (RX) section of the CYP(V)(W)15G0101DXB
Single-channel HOTLink II consists of a byte-wide channel.
The channel accepts a serial bit-stream from one of two
PECL-compatible differential Line Receivers and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. The
recovered bit-stream is deserialized and framed into
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system. The integrated 8B/10B Encoder/Decoder may be
bypassed for systems that present externally encoded or
scrambled data at the parallel interface.
TXD[7:0]
TXCT[1:0]
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path interfaces
from one or multiple sources, the receive interface may be
configured to present data relative to a recovered clock or to a
local reference clock.
The transmit and the receive channels contain BIST pattern
generators and checkers, respectively. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
both transmit and receive sections, as well as across the inter-
connecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting
backplanes
on
switches,
routers,
base-stations, servers and video transmission systems.
The CYV15G0101DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol-
lowed by 1 one.
x10
Phase
Align
Buffer
Encoder
8B/10B
Elasticity
Buffer
Decoder
8B/10B
Framer
Serializer
Deserializer
TX
OUT1±
OUT2±
Document #: 38-02031 Rev. *J
IN1±
IN2±
RXD[7:0]
RXST[2:0]
x11
Transceiver Logic Block Diagram
RX
Page 2 of 39
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Logic Block Diagram
REFCLK+
REFCLK–
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
TXPER
Phase-Align
Buffer
Input
Register
12
12
12
BIST LFSR
8B/10B
SCSEL
TXD[7:0]
TXOP
TXCT[1:0]
TXCKSEL
TXCLK
TXRST
PARCTL
BOE[1:0]
BIST Enable
Latch
8
2
10
OUT1+
OUT1–
OUT2+
OUT2–
TXLB
= Internal Signal
TRSTZ
Character-Rate Clock
Transmit PLL
Clock Multiplier
Character-Rate Clock
Bit-Rate Clock
2
Transmit
Mode
H M L
Shifter
Parity
Check
4
Output
Enable
Latch
2
OELE
RXLE
RX PLL Enable
Latch
BISTLE
Character-Rate Clock
SDASEL
LPEN
INSEL
IN1+
IN1–
IN2+
IN2–
TXLB
FRAMCHAR
RFEN
RFMODE
DECMODE
RXRATE
RXMODE
RXCKSEL
JTAG
Boundary
Scan
Controller
TMS
TCLK
TDI
TDO
Receive
Signal
Monitor
Framer
Clock &
Data
Recovery
PLL
Shifter
LFI
Elasticity
Buffer
10B/8B
BIST
Output
Register
8
3
RXD[7:0]
RXOP
RXST[2:0]
RXCLK+
RXCLK–
Delay
RXCLKC+
Clock
Select
÷2
Document #: 38-02031 Rev. *J
Page 3 of 39
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Pin Configuration
Top View
1
A
B
C
D
E
F
G
H
J
K
V
CC
V
CC
RFEN
BOE[0]
BISTLE
RXST[2]
RXOP
RXD[0]
V
CC
V
CC
2
IN2+
IN2–
LPEN
BOE[1]
DECMOD
E
RXST[1]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
3
V
CC
TDO
RXLE
FRAMCHA
R
OELE
RXST[0]
RXD[5]
RXD[6]
RXD[7]
V
CC
4
OUT2–
OUT2+
5
6
7
IN1+
IN1–
SPDSEL
GND
GND
GND
GND
TXD[3]
TXD[2]
TXD[1]
8
V
CC
#NC
[2]
9
OUT1–
OUT1+
10
V
CC
V
CC
INSEL
TDI
RXMODE TXMODE[1]
TXRATE TXMODE[0]
SDASEL
GND
GND
GND
GND
TXD[6]
TXD[5]
TXD[4]
RXCLKC+ RXRATE
GND
GND
GND
GND
LFI
RXCLK–
RXCLK+
GND
GND
GND
GND
TXCT[1]
TXCT[0]
TXD[7]
Bottom View
PARCTL RFMODE
TMS
TCLK
TXPER
TXOP
TXCLK
TXD[0]
V
CC
TRSTZ
RXCKSEL TXCKSEL
REFCLK– REFCLK+
TXCLKO+ TXCLKO–
TXRST
#NC
[2]
SCSEL
#NC
[2]
V
CC
V
CC
10
V
CC
V
CC
INSEL
TDI
9
OUT1–
OUT1+
8
V
CC
#NC
[2]
7
IN1+
IN1–
SPDSEL
GND
GND
GND
GND
TXD[3]
TXD[2]
TXD[1]
6
5
4
OUT2–
OUT2+
3
V
CC
TDO
RXLE
FRAMCHA
R
OELE
RXST[0]
RXD[5]
RXD[6]
RXD[7]
V
CC
2
IN2+
IN2–
LPEN
BOE[1]
DECMOD
E
RXST[1]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
1
V
CC
V
CC
RFEN
BOE[0]
BISTLE
RXST[2]
RXOP
RXD[0]
V
CC
V
CC
A
B
C
D
E
F
G
H
J
K
TXMODE[1] RXMODE
TXMODE[0] TXRATE
SDASEL
GND
GND
GND
GND
TXD[6]
TXD[5]
TXD[4]
RFMODE PARCTL
TRSTZ
TMS
TCLK
TXPER
TXOP
TXCLK
TXD[0]
V
CC
RXRATE RXCLKC+
GND
GND
GND
GND
TXCT[1]
TXCT[0]
TXD[7]
GND
GND
GND
GND
LFI
RXCLK–
RXCLK+
TXCKSEL RXCKSEL
REFCLK+ REFCLK–
TXCLKO– TXCLKO+
#NC
[2]
V
CC
V
CC
TXRST
#NC
[2]
SCSEL
Note:
2. #NC = Do Not Connect.
Document #: 38-02031 Rev. *J
Page 4 of 39
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Pin Descriptions
CYP(V)(W)15G0101DXB Single-channel HOTLink II
Pin Name
TXPER
I/O Characteristics Signal Description
LVTTL Output,
changes relative to
REFCLK↑
[3]
Transmit Path Parity Error.
Active HIGH. Asserted (HIGH) if parity checking is enabled
(PARCTL
≠
LOW) and a parity error is detected at the Encoder. This output is HIGH for one
transmit character-clock period to indicate detection of a parity error in the character
presented to the Encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to force
a corresponding bad-character detection at the remote end of the link. This replacement
takes place regardless of the encoded/un-encoded state of the interface.
When BIST is enabled for the specific transmit channel, BIST progress is presented on this
output. Once every 511 character times (plus a 16-character Word Sync Sequence when
the receive channel is clocked by REFCLK, i.e., RXCKSEL = LOW), the TXPER signal
pulses HIGH for one transmit-character clock period (if RXCKSEL = MID) or seventeen
transmit-character clock periods (if RXCKSEL = LOW or HIGH) to indicate a complete pass
through the BIST sequence. For RXCKSEL = LOW or HIGH, If TXMODE[1:0] = LL, then no
Word Sync Sequence is sent in BIST, and TXPER pulses HIGH for one transmit-character
clock period.
This output also provides an indication of a Phase-Align Buffer underflow/overflow
condition. When the Phase-Align Buffer is enabled (TXCKSEL
≠
LOW, or TXCKSEL = LOW
and TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted
and remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is
sampled LOW to recenter the Phase-Align Buffer.
TXCT[1:0]
LVTTL Input,
synchronous,
sampled by TXCLK↑
or REFCLK↑
[3]
Transmit Control.
These inputs are captured on the rising edge of the transmit interface
clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They
identify how the TXD[7:0] characters are interpreted. When the Encoder is enabled, these
inputs determine if the TXD[7:0] character is encoded as Data, a Special Character code,
a K28.5 fill character or a Word Sync Sequence. When the Encoder is bypassed, these
inputs are interpreted as data bits. See
Table 1
for details.
Transmit Data Inputs.
These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL, and passed to the Encoder or Transmit Shifter.
When the Encoder is enabled (TXMODE[1]
≠
LOW), TXD[7:0] specify the specific data or
command character to be sent. When the Encoder is bypassed, these inputs are interpreted
as data bits of the 10-bit input character. See
Table 1
for details.
Transmit Path Data Signals
TXD[7:0]
LVTTL Input,
synchronous,
sampled by TXCLK↑
or REFCLK↑
[3]
TXOP
LVTTL Input,
Transmit Path Odd Parity.
When parity checking is enabled (PARCTL
≠
LOW), the parity
synchronous,
captured at this input is XORed with the data on the TXD bus (and sometimes TXCT[1:0])
internal pull-up,
to verify the integrity of the captured character. See
Table 2
for details.
sampled by TXCLK↑
or REFCLK↑
[3]
LVTTL Input,
synchronous,
internal pull-down,
sampled by TXCLK↑
or REFCLK↑
[3]
Special Character Select.
Used in some transmit modes along with TXCTx[1:0] to encode
special characters or to initiate a Word Sync Sequence. When the transmit path is
configured to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL
is captured relative to TXCLK↑.
=
HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges
SCSEL
Note:
3. When REFCLK is configured for half-rate operation (TXRATE
of REFCLK.
Document #: 38-02031 Rev. *J
Page 5 of 39
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