EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

BD033-090-A-S-0-0610-0630-L-E

Description
Board Connector, 90 Contact(s), 2 Row(s), Male, Straight, 0.05 inch Pitch, Surface Mount Terminal, Locking, Black Insulator,
CategoryThe connector    The connector   
File Size110KB,1 Pages
ManufacturerGlobal Connector Technology
Environmental Compliance
Download Datasheet Parametric View All

BD033-090-A-S-0-0610-0630-L-E Overview

Board Connector, 90 Contact(s), 2 Row(s), Male, Straight, 0.05 inch Pitch, Surface Mount Terminal, Locking, Black Insulator,

BD033-090-A-S-0-0610-0630-L-E Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid1948620583
Reach Compliance Codecompliant
Country Of OriginMainland China
ECCN codeEAR99
YTEOL8.75
body width0.222 inch
subject depth0.224 inch
body length2.376 inch
Connector typeBOARD STACKING CONNECTOR
Contact to complete cooperationGOLD FLASH
Contact completed and terminatedGOLD OVER NICKEL
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
contact modeRECTANGULAR
Contact resistance20 mΩ
Contact styleSQ PIN-SKT
DIN complianceNO
Dielectric withstand voltage300VAC V
Filter functionNO
IEC complianceNO
Insulation resistance1000000000 Ω
Insulator colorBLACK
insulator materialLIQUID CRYSTAL POLYMER
JESD-609 codee4
MIL complianceNO
Plug contact pitch0.05 inch
Match contact row spacing0.05 inch
Plug informationMULTIPLE MATING PARTS AVAILABLE
Mixed contactsNO
Installation option 1LOCKING
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number2
Number of rows loaded2
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
OptionsGENERAL PURPOSE
PCB contact patternRECTANGULAR
PCB contact row spacing4.4 mm
Plating thicknessFLASH inch
polarization keyPOLARIZED HOUSING
Rated current (signal)1 A
GuidelineUL
Terminal pitch1.27 mm
Termination typeSURFACE MOUNT
Total number of contacts90
UL Flammability Code94V-0
[Technical question] How to implement low power (upf) design using FPGA?
How to implement low power (upf) design using FPGA ? Low power design is used in chip design. DC synthesis will read in upf files and generate special units, such as level shift, isolation, retention ...
eeleader FPGA/CPLD
STM Network Academy--Learning Platform Program Collection (Continuously Updated)
Support the OP! Good stuff!...
bigsmartboy stm32/stm8
EEWORLD University Hall----Live Replay: TI millimeter wave radar application in industry
Live replay: TI mmWave radar applications in industry : https://training.eeworld.com.cn/course/4692...
hi5 Integrated technical exchanges
EEWORLD DIY-Software Defined Radio Active Learning Platform (1 Introduction)
[i=s]This post was last edited by 不足论 on 2017-10-26 11:50[/i] Item Introduction: [url=https://wiki.analog.com/university/tools/pluto]https://wiki.analog.com/university/tools/pluto[/url]I am a pure cod...
不足论 DIY/Open Source Hardware
T-BOX System Solution In-depth Analysis of Interfaces
[i=s]This post was last edited by alan000345 on 2018-10-17 09:11[/i] [align=center][color=rgb(85, 85, 85)][font="][size=14px][b]Section 3 Interface[/b][/size][/font][/color][/align][align=left][color=...
alan000345 TI Technology Forum
Embedded computers lead the new era of weapons and equipment
Computers are the soul of information-based and intelligent weapon systems. For quite a long time, weapons and their computers were basically self-contained systems. Since the emergence of microcomput...
程序天使 Industrial Control Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2797  1704  1620  2167  1668  57  35  33  44  34 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号