NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY
(LSB)
±8
DIFFERENTIAL
NONLINEARITY
(LSB)
±1
SPECIFIED
TEMPERATURE
RANGE
–40°C to +105°C
PRODUCT
DAC7512E
PACKAGE-LEAD
MSOP-8
PACKAGE
DESIGNATOR
(1)
DGK
PACKAGE
MARKING
D12E
ORDERING
NUMBER
(1)
DAC7512E/250
DAC7512E/2K5
DAC7512N/250
DAC7512N/3K
TRANSPORT
MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
"
DAC7512N
"
±8
"
±1
"
SOT23-6
"
DBV
"
–40°C to +105°C
"
D12N
"
"
"
"
"
"
"
NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape
and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7512E/2K5” will get a single 2500-piece Tape and Reel.
PIN CONFIGURATIONS
Top View
V
OUT
GND
V
DD
1
2
3
DAC7512
SOT23-6
6
5
4
SYNC
SCLK
D
IN
PIN DESCRIPTION (SOT23-6)
PIN
1
2
3
4
NAME
V
OUT
GND
V
DD
D
IN
DESCRIPTION
Analog output voltage from DAC. The output ampli-
fier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Power Supply Input, +2.7V to 5.5V.
Serial Data Input. Data is clocked into the 16-bit
input shift register on the falling edge of the serial
clock input.
Serial Clock Input. Data can be transferred at rates
up to 30MHz.
Level triggered control input (active LOW). This is
the frame sychronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred in on the falling
edges of the following clocks. The DAC is updated
following the 16th clock cycle unless SYNC is taken
HIGH before this edge, in which case the rising
edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC7512.
MSOP-8
V
DD
NC
NC
V
OUT
1
2
DAC7512
3
4
6
5
8
7
GND
D
IN
SCLK
SYNC
5
6
SCLK
SYNC
NC = No Internal Connection
DAC7512N LOT TRACE LOCATION
Top View
Pin 1
Bottom View
D12N
Pin 1
YMLL
Lot Trace Code
2
DAC7512
www.ti.com
SBAS156B
ELECTRICAL CHARACTERISTICS
V
DD
= +2.7V to +5.5V; R
L
= 2k½ to GND; C
L
= 200pF to GND.
DAC7512E, N
PARAMETER
STATIC PERFORMANCE
(1)
Resolution
Relative Accuracy
Differential Nonlinearity
Zero Code Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
(2)
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
LSB
LSB
mV
% of FSR
% of FSR
µV/°C
ppm of FSR/°C
V
µs
µs
V/µs
pF
pF
nV-s
nV-s
Ω
mA
mA
µs
µs
Tested Monotonic by Design
All Zeroes Loaded to DAC Register
All Ones Loaded to DAC Register
+5
–0.15
–20
–5
0
±8
±1
+20
–1.25
±1.25
V
DD
8
12
10
1/4 Scale to 3/4 Scale Change
(400
H
to C00
H
)
R
L
= 2kΩ; 0pF < C
L
< 200pF
R
L
= 2kΩ; C
L
= 500pF
1
R
L
= ×
R
L
= 2kΩ
1LSB Change Around Major Carry
Slew Rate
Capacitive Load Stability
Code Change Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
Power-Up Time
V
DD
= +5V
V
DD
= +3V
Coming Out of Power-Down Mode
V
DD
= +5V
Coming Out of Power-Down Mode
V
DD
= +3V
470
1000
20
0.5
1
50
20
2.5
5
±1
0.8
0.6
2.4
2.1
3
2.7
5.5
135
115
0.2
0.05
93
–40
+105
200
160
1
1
LOGIC INPUTS
(2)
Input Current
V
IN
L, Input Low Voltage
V
IN
L, Input Low Voltage
V
IN
H, Input High Voltage
V
IN
H, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(normal mode)
V
DD
= +3.6V to +5.5V
V
DD
= +2.7V to +3.6V
I
DD
(all power-down modes)
V
DD
= +3.6V to +5.5V
V
DD
= +2.7V to +3.6V
POWER EFFICIENCY
I
OUT
/I
DD
TEMPERATURE RANGE
Specified Performance
V
DD
V
DD
V
DD
V
DD
=
=
=
=
+5V
+3V
+5V
+3V
µA
V
V
V
V
pF
V
µA
µA
µA
µA
%
°C
DAC Active and Excluding Load Current
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
I
LOAD
= 2mA. V
DD
= +5V
NOTES: (1) Linearity calculated using a reduced code range of 48 to 4047; output unloaded. (2) Guaranteed by design and characterization, not production tested.
DAC7512
SBAS156B
www.ti.com
3
TIMING CHARACTERISTICS
(1, 2)
V
DD
= +2.7V to +5.5V; all specifications –40°C to +105°C, unless otherwise noted.
DAC7512E, N
PARAMETER
t
1(3)
DESCRIPTION
SCLK Cycle Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
2
SCLK HIGH Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
3
SCLK LOW Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
4
SYNC to SCLK Rising
Edge Setup Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
5
Data Setup Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
6
Data Hold Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
7
SCLK Falling Edge to
SYNC Rising Edge
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
t
8
Minimum SYNC HIGH Time
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
50
33
ns
ns
0
0
ns
ns
4.5
4.5
ns
ns
5
5
ns
ns
0
0
ns
ns
22.5
13
ns
ns
13
13
ns
ns
50
33
ns
ns
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES: (1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. (2) See Serial Write Operation timing
diagram, below. (3) Maximum SCLK frequency is 30MHz at V
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