Burr Brown Products
from Texas Instruments
DA
C8
555
®
DAC8555
SLAS475A – NOVEMBER 2005 – REVISED DECEMBER 2005
16-BIT, QUAD CHANNEL, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
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Relative Accuracy: 12 LSB (Max)
Glitch Energy: 0.15 nV-s
Power Supply: +2.7 V to +5.5 V
MicroPower
Operation: 850 µA at 5 V
16-Bit Monotonic Over Temperature
Settling Time: 10 µs to
±0.003%
FSR
Power-On Reset to Zero-Scale and Mid-Scale
Binary and 2's Complement Capability
Ultra-Low AC Crosstalk: –100 dB Typ
On-Chip Output Buffer Amplifier With
Rail-to-Rail Operation
Double Buffered Input Architecture
Simultaneous or Sequential Output Update
and Power-Down
Asynchronous Clear to Zero-Scale and
Mid-Scale
Schmitt-Triggered Inputs
SPI Compatible Serial Interface: Up to 50 MHz.
1.8 V to 5.5 V Logic Compatibility
Available in a TSSOP-16 Package
DESCRIPTION
The DAC8555 is a 16-bit, quad channel voltage
output digital-to-analog converter (DAC) offering
low-power operation and a flexible serial host
interface. It offers monotonicity, good linearity, and
exceptionally low glitch. Each on-chip precision
output amplifier allows rail-to-rail output swing to be
achieved over the supply range of 2.7 V to 5.5 V. The
device supports a standard 3-wire serial interface
capable of operating with input data clock frequencies
up to 50 MHz for IOV
DD
= 5 V.
The DAC8555 requires an external reference voltage
to set the output range of each DAC channel. Also
incorporated into the device is a power-on reset
circuit which can be programmed to ensure that the
DAC outputs power up at zero-scale or mid-scale and
remain there until a valid write takes place. The
device also has the capability to function in both
binary and 2's complement mode. The DAC8555
provides a per channel power-down feature,
accessed over the serial interface, that reduces the
current consumption to 200 nA per channel at 5 V.
The low-power consumption of this device in normal
operation makes it ideally suited to portable battery-
operated
equipment
and
other
low-power
applications. The power consumption is 5 mW at 5 V,
reducing to 4 µW in power-down mode.
The DAC8555 is available in a TSSOP-16 package
with a specified operating temperature range of
–40°C to 105°C.
APPLICATIONS
Portable Instrumentation
Closed-Loop Servo-Control
Process Control
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC8555
www.ti.com
SLAS475A – NOVEMBER 2005 – REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
AV
DD
IOV
DD
V
REF
H
Data
Buffer A
DAC
Register A
DAC A
V
OUT
A
V
OUT
B
V
OUT
C
18
Data
Buffer D
DAC
Register D
DAC D
V
OUT
D
SYNC
SCLK
D
IN
24-Bit
Serial-to-
Parallel Shift
Register
8
Buffer
Control
Register
Control
Power-Down
Control Logic
Resistor
Network
RST RSTSEL
LDAC
ENABLE
V
REF
L
PACKAGING/ORDERING INFORMATION
PRODUCT
DAC8555
PACKAGE
LEAD
TSSOP-16
PACKAGE
DESIGNATOR
(1)
PW
SPECIFICATION
TEMPERATURE RANGE
–40°C TO 105°C
PACKAGE
MARKING
D8555
ORDERING
NUMBER
DAC8555IPW
DAC8555IPWR
TRANSPORT
MEDIA, QUANTITY
Tube, 90
Tape and Reel, 2000
(1)
For the most current specifications and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
UNIT
AV
DD
, IOV
DD
to GND
Digital input voltage to GND
V
O(A)
to V
O(D)
to GND
Operating temperature range
Storage temperature range
Junction temperature range (T
J
max)
Power dissipation
θ
JA
Thermal impedance
θ
JC
Thermal impedance
(1)
–0.3 V to 6 V
–0.3 V to +AV
DD
+ 0.3 V
–0.3 V to +AV
DD
+ 0.3 V
–40°C to 105°C
–65°C to 150°C
150°C
(T
J
max – T
A
)/θ
JA
118°C/W
29°C/W
Stresses above those listed under
absolute maximum ratings
may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
DAC8555
www.ti.com
SLAS475A – NOVEMBER 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
(1)
Resolution
Relative accuracy
Differential nonlinearity
Zero-scale error
Zero-scale error drift
Full-scale error
Gain error
Gain temperature coefficient
Power Supply Rejection Ratio
(PSRR)
OUTPUT
CHARACTERISTICS
(2)
0
To ±0.003% FSR, 0200
H
to FD00
H
, R
L
= 2 kΩ, 0 pF
< C
L
< 200 pF
R
L
= 2 kΩ, C
L
= 500 pF
Slew rate
Capacitive load stability
Code change glitch impulse
Digital feedthrough
DC crosstalk
AC crosstalk
DC output impedance
Short-circuit current
Power-up time
AC PERFORMANCE
SNR (1st 19 harmonics removed)
THD
SFDR
SINAD
REFERENCE INPUT
V
ref(H)
Voltage
V
ref(L)
Voltage
Reference input current
Reference input impedance
V
ref(L)
< V
ref(H)
, AV
DD
- (V
ref(H)
+ V
ref(L)
) /2 > 1.2 V
V
ref(L)
< V
ref(H)
, AV
DD
- (V
ref(H)
+ V
ref(L)
) /2 > 1.2 V
V
ref(L)
= GND, V
ref(H)
= AV
DD
= 5 V
V
ref(L)
= GND, V
ref(H)
= AV
DD
= 3 V
V
ref(L)
< V
ref(H)
0
0
180
120
31
AV
DD
AV
DD
/2
250
200
V
V
µA
µA
kΩ
BW = 20 kHz, AV
DD
= 5 V, F
OUT
= 1 kHz
95
-85
87
84
dB
Full-scale swing on adjacent channel. AV
DD
= 5 V,
V
ref
= 4.096 V
1 kHz sine wave
At mid-point input
AV
DD
= 5 V
AV
DD
= 3 V
Coming out of power-down mode AV
DD
= 5 V
Coming out of power-down mode AV
DD
= 3 V
R
L
=
∞
R
L
= 2 kΩ
1 LSB change around major carry
8
12
1.8
470
1000
0.15
0.15
0.25
–100
1
50
20
2.5
5
V
ref
H
10
V
µs
µs
V/µs
pF
pF
nV-s
LSB
dB
Ω
mA
µs
R
L
= 2 kΩ, C
L
= 200 pF
Measured by line passing through codes 485 and
64741, AV
DD
= 5 V, V
ref
= 4.99 V
Measured by line passing through codes 485 and
64741, AV
DD
= 5 V
Measured by line passing through codes 485 and
64741
16-bit Monotonic
Measured by line passing through codes 485 and
64741
16
±4
±0.25
±2
±5
±0.3
±0.05
±1
8
0.75
±0.5
±0.15
±12
±1
±12
Bits
LSB
LSB
mV
µV/°C
% of FSR
% of FSR
ppm of FSR/°C
mV
mV/V
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage range
Output voltage settling time
(1)
(2)
Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
Ensured by design and characterization, not production tested.
3
DAC8555
www.ti.com
SLAS475A – NOVEMBER 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
LOGIC INPUTS
(2)
TEST CONDITIONS
MIN
TYP
MAX
0.3
×
I0V
DD
0.1
×
I0V
DD
UNIT
2.7 V
≤
IOV
DD
≤
5.5 V
V
I(L)
, logic input LOW voltage
1.8 V
≤
IOV
DD
≤
2.7 V
2.7
≤
IOV
DD
≤
5.5 V
V
I(H)
, logic input HIGH voltage
1.8
≤
IOV
DD
< 2.7 V
0.7
×
I0V
DD
0.95
×
I0V
DD
V
V
Pin capacitance
POWER REQUIREMENTS
AV
DD
IOV
DD
AI
DD
(normal mode)
IOI
DD
AV
DD
= 3.6 V to 5.5 V
AV
DD
= 2.7 V to 3.6 V
AI
DD
(all power-down modes)
AV
DD
= 3.6 V to 5.5 V
AV
DD
= 2.7 V to 3.6 V
POWER EFFICIENCY
I
OUT
/I
DD
TEMPERATURE RANGE
Specified performance
–40
I
L
= 2 mA, AV
DD
= 5 V
89%
V
IH
= IOV
DD
and V
IL
= GND
0.2
0.05
V
IH
= IOV
DD
and V
IL
= GND
Input code = 32768, no load
10
0.65
0.6
2.7
1.8
3
5.5
5.5
20
0.95
0.9
2
2
pF
V
µA
mA
µA
105
°C
PIN CONFIGURATION
V
OUT
A
V
OUT
B
V
REF
H
AV
DD
V
REF
L
GND
V
OUT
C
V
OUT
D
1
2
3
4
DAC8555
5
6
7
8
12 IOV
DD
11 D
IN
10 SCLK
9
SYNC
16 LDAC
15 ENABLE
14 RSTSEL
13 RST
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
4
NAME
V
OUT
A
V
OUT
B
V
ref
H
AV
DD
V
ref
L
GND
V
OUT
C
Analog output voltage from DAC A.
Analog output voltage from DAC B.
Positive reference voltage input.
Power supply input, 2.7 V to 5.5 V.
Negative reference voltage input.
Ground reference point for all circuitry on the part.
Analog output voltage DAC C.
DESCRIPTION
DAC8555
www.ti.com
SLAS475A – NOVEMBER 2005 – REVISED DECEMBER 2005
PIN DESCRIPTIONS (continued)
PIN
8
NAME
V
OUT
D
Analog output voltage DAC D.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When
SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the
DAC8555).
Serial clock input. Data can be transferred at rates up to 50 MHz.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
input.
Digital input-output power supply
Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero scale (RSTSEL = 0) or to
midscale (RSTSEL = 1).
Reset select. If RSTSEL is low, input coding is binary; if high = 2's complement.
Active LOW, ENABLE LOW connects the SPI interface to the serial port.
Load DACs, rising edge triggered loads all DAC registers.
DESCRIPTION
9
SYNC
10
11
12
13
14
15
16
SCLK
D
IN
IOV
DD
RST
RSTSEL
ENABLE
LDAC
TIMING REQUIREMENTS
(1) (2)
AV
DD
= 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER
t
1 (3)
SCLK cycle time
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
SCLK HIGH time
SCLK LOW time
SYNC falling edge to SCLK rising edge setup time
Data setup time
Data hold time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
24th SCLK falling edge to SYNC falling edge
Miniumum RST low time
TEST CONDITIONS
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.6 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 5.5 V
IOV
DD
= AV
DD
= 2.7 V to 3.5 V
IOV
DD
= AV
DD
= 3.6 V to 5.5 V
MIN
40
20
20
10
20
10
0
0
5
5
4.5
4.5
0
0
40
20
130
40
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
(2)
(3)
All input signals are specified with t
R
= t
F
= 3 ns (10% to 90% of AV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See Serial Write Operation timing diagram.
Maximum SCLK frequency is 50 MHz at IOV
DD
= AV
DD
= 3.6 V to 5.5 V and 25 MHz at IOV
DD
= AV
DD
= 2.7 V to 3.6 V.
5
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