The DAC7615 is a quad, serial input, 12-bit, voltage
output digital-to-analog converter (DAC) with guar-
anteed 12-bit monotonic performance over the –40°C
to +85°C temperature range. An asynchronous reset
clears all registers to either mid-scale (800
H
) or zero-
scale (000
H
), selectable via the RESETSEL pin. The
individual DAC inputs are double buffered to allow
GND
for simultaneous update of all DAC outputs. The
device can be powered from a single +5V supply or
from dual +5V and –5V supplies.
Low power and small size makes the DAC7615 ideal
for automatic test equipment, DAC-per-pin program-
mers, data acquisition systems, and closed-loop servo-
control. The device is available in 16-pin plastic DIP,
16-lead SOIC, and 20-lead SSOP packages and is
guaranteed over the –40°C to +85°C temperature range.
V
DD
V
REFH
Input
Register A
SDI
DAC
Register A
DAC A
V
OUTA
Serial-to-
Parallel
Shift
Register
Input
Register B
12
DAC
Register B
DAC B
V
OUTB
Input
Register C
DAC
Register C
DAC C
V
OUTC
CLK
CS
DAC
Select
Input
Register D
DAC
Register D
DAC D
V
OUTD
LOADREG
RESETSEL RESET
LOADDACS
V
REFL
V
SS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
and above. (2) LSB means Least Significant Bit, with V
REFH
equal to +2.5V and V
REFL
equal to –2.5V,
one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.
(5) If V
SS
= –5V, full-scale step from code 000
H
to FFF
H
or vice-versa. If V
SS
= 0V, full-scale positive step from code 000
H
to FFF
H
and negative step from code
FFF
H
to 00A
H
.
–40
+85
°C
–2.1
If V
SS
≠
0V
4.75
–5.25
1.5
–1.6
15
7.5
5.25
–4.75
1.9
V
V
mA
mA
mW
mW
| I
IH
|
≤
10µA
| I
IL
|
≤
10µA
2.4
–0.3
Straight Binary
V
DD
+0.3
0.8
TTL-Compatible CMOS
To
±0.012%
Full-Scale Step
On Any Other DAC, R
L
= 2kΩ
Bandwidth: 0Hz to 1MHz
40
nV/√Hz
5
0.1
10
µs
LSB
V
SS
= 0V or –5V
V
SS
= 0V
V
SS
= –5V
V
REFL
+1.25
0
–2.5
+2.5
V
REFH
–1.25
V
REFH
–1.25
V
V
V
No Oscillation
V
SS
= 0V or –5V
V
REFL
–1.25
100
+5, –15
Indefinite
V
REFH
+1.25
T
T
V
mA
pF
mA
Code = FFF
H
Code = 000
H
2
V
SS
= 0V or –5V
V
SS
= 0V or –5V
V
SS
= 0V or –5V
12
±4
5
±2
±4
±2
±8
10
±4
±8
±4
T
T
T
±2
±2
±1
T
T
T
±1
T
±1
T
T
±2
T
±2
±1
±1
±1
LSB
(2)
LSB
LSB
Bits
LSB
ppm/°C
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
LSB
ppm/V
CONDITIONS
MIN
TYP
MAX
DAC7615EB, PB, UB
MIN
TYP
MAX
UNITS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7615
2
ABSOLUTE MAXIMUM RATINGS
(1)
V
DD
to V
SS
........................................................................... –0.3V to +11V
V
DD
to GND ........................................................................ –0.3V to +5.5V
V
REFL
to V
SS
............................................................... –0.3V to (V
DD
– V
SS
)
V
DD
to V
REFH
.............................................................. –0.3V to (V
DD
– V
SS
)
V
REFH
to V
REFL
............................................................ –0.3V to (V
DD
– V
SS
)
Digital Input Voltage to GND ...................................... –0.3V to V
DD
+ 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM
LINEARITY
ERROR
(LSB)
±2
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
±1
PACKAGE
DRAWING
NUMBER
(1)
180
SPECIFICATION
TEMPERATURE
RANGE
–40°C to +85°C
PRODUCT
DAC7615P
DAC7615PB
DAC7615U
PACKAGE
16-Pin DIP
ORDERING
NUMBER
(2)
DAC7615P
DAC7615PB
DAC7615U
DAC7615U/1K
DAC7615UB
DAC7615UB/1K
DAC7615E
DAC7615E/1K
DAC7615EB
DAC7615EB/1K
TRANSPORT
MEDIA
Rails
Rails
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
"
±2
"
±1
"
16-Lead SOIC
"
211
"
–40°C to +85°C
"
DAC7615UB
"
±1
"
±1
"
16-Lead SOIC
"
211
"
–40°C to +85°C
"
DAC7615E
"
±2
±1
"
±1
±1
"
20-Lead SSOP
"
334
"
–40°C to +85°C
"
DAC7615EB
"
"
"
"
"
20-Lead SSOP
"
334
"
–40°C to +85°C
"
"
"
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7615EB/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
DAC7615
PIN CONFIGURATION—P, U Packages
Top View
PDIP, SOIC
PIN CONFIGURATION—E Package
Top View
SSOP
V
DD
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
V
SS
1
2
3
4
5
6
7
8
DAC7615P, U
16
15
14
13
12
11
10
9
RESETSEL
RESET
LOADREG
LOADDACS
CS
CLK
SDI
GND
V
DD
V
OUTD
V
OUTC
V
REFL
NIC
NIC
V
REFH
V
OUTB
V
OUTA
1
2
3
4
5
DAC7615E
6
7
8
9
20
19
18
17
16
15
14
13
12
11
RESETSEL
RESET
LOADREG
LOADDACS
NIC
NIC
CS
CLK
SDI
GND
V
SS
10
PIN DESCRIPTIONS—P, U Packages
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
LABEL
V
DD
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
V
SS
GND
SDI
CLK
CS
LOADDACS
DESCRIPTION
Positive Analog Supply Voltage, +5V nominal.
DAC D Voltage Output
DAC C Voltage Output
Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
DAC B Voltage Output
DAC A Voltage Output
Negative Analog Supply Voltage, 0V or –5V nomi-
nal.
Ground
Serial Data Input
Serial Data Clock
Chip Select Input
All DAC registers become transparent when
LOADDACS is LOW. They are in the latched state
when LOADDACS is HIGH.
The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
Asynchronous Reset Input. Sets DAC and input
registers to either zero-scale (000
H
) or mid-scale
(800
H
) when LOW. RESETSEL determines which
code is active.
When LOW, a LOW on RESET will cause the DAC
and input registers to be set to code 000
H
. When
RESETSEL is HIGH, a LOW on RESET will set the
registers to code 800
H
.
PIN DESCRIPTIONS—E Package
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
LABEL
V
DD
V
OUTD
V
OUTC
V
REFL
NIC
NIC
V
REFH
V
OUTB
V
OUTA
V
SS
GND
SDI
CLK
CS
NIC
NIC
LOADDACS
DESCRIPTION
Positive Analog Supply Voltage, +5V nominal.
DAC D Voltage Output
DAC C Voltage Output
Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
Not Internally Connected.
Not Internally Connected.
Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
DAC B Voltage Output
DAC A Voltage Output
Negative Analog Supply Voltage, 0V or –5V nomi-
nal.
Ground
Serial Data Input
Serial Data Clock
Chip Select Input
Not Internally Connected.
Not Internally Connected.
All DAC registers becomes transparent when
LOADDACS is LOW. They are in the latched state
when LOADDACS is HIGH.
The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
Asynchronous Reset Input. Sets all DAC registers
to either zero-scale (000
H
) or mid-scale (800
H
)
when LOW. RESETSEL determines which code is
active.
When LOW, a LOW on RESET will cause all DAC
registers to be set to code 000
H
. When RESETSEL
is HIGH, a LOW on RESET will set the registers to
code 800
H
.
14
LOADREG
15
RESET
16
RESETSEL
18
LOADREG
19
RESET
20
RESETSEL
®
DAC7615
4
TYPICAL PERFORMANCE CURVES: V
SS
= 0V
At T
A
= +25°C, V
DD
= +5V, V
SS
= 0V, V
REFH
= +2.5V, and V
REFL
= 0V, representative unit, unless otherwise specified.
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