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MT42L192M64D3LP-25AT:A

Description
DDR DRAM, 192MX64, CMOS, PBGA216, 12 X 12 MM, 0.82 MM HEIGHT, 0.40 MM PITCH, GREEN, FBGA-216
Categorystorage    storage   
File Size2MB,172 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT42L192M64D3LP-25AT:A Overview

DDR DRAM, 192MX64, CMOS, PBGA216, 12 X 12 MM, 0.82 MM HEIGHT, 0.40 MM PITCH, GREEN, FBGA-216

MT42L192M64D3LP-25AT:A Parametric

Parameter NameAttribute value
MakerMicron Technology
package instructionVFBGA,
Reach Compliance Codecompliant
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Other featuresSELF REFRESH; IT ALSO REQUIRES 1.2V NOM
JESD-30 codeS-PBGA-B216
length12 mm
memory density12884901888 bit
Memory IC TypeDDR DRAM
memory width64
Number of functions1
Number of ports1
Number of terminals216
word count201326592 words
character code192000000
Operating modeSYNCHRONOUS
organize192MX64
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeSQUARE
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Maximum seat height0.82 mm
self refreshYES
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch0.4 mm
Terminal locationBOTTOM
width12 mm
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Mobile LPDDR2 SDRAM
MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,
MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,
MT42L256M64D4, MT42L384M32D3
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade
(MHz)
(Mb/s/pin)
-18
-25
-3
533
400
333
1066
800
667
RL
8
6
5
WL
4
3
2
t
RCD/
t
RP
1
Options
Marking
Typical
Typical
Typical
• V
DD2
: 1.2V
L
• Configuration
– 32 Meg x 16 x 8 banks x 1 die
256M16
– 16 Meg x 32 x 8 banks x 1 die
128M32
– 16 Meg x 32 x 8 banks x 2 die
256M32
– 1 (16 Meg x 32 x 8 banks) + 2 (32
384M32
Meg x 16 x 8 banks)
– 32 Meg x 16 x 8 banks x 4 die
512M32
– 16 Meg x 32 x 8 banks x 2 die
128M64
– 16 Meg x 32 x 8 banks x 3 die
192M64
– 16 Meg x 32 x 8 banks x 4 die
256M64
• Device type
– LPDDR2-S4, 1 die in package
D1
– LPDDR2-S4, 2 die in package
D2
– LPDDR2-S4, 3 die in package
D3
– LPDDR2-S4, 4 die in package
D4
• FBGA “green” package
– 134-ball FBGA (10mm x
GU, GV
11.5mm)
– 168-ball FBGA (12mm x 12mm)
LF, LG
– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,
LP
– 220-ball FBGA (14mm x 14mm)
LD, MP
– 240-ball FBGA (14mm x 14mm)
MC
– 253-ball FBGA (11mm x 11mm)
EU, EV
• Timing – cycle time
– 1.875ns @ RL = 8
-18
– 2.5ns @ RL = 6
-25
– 3.0ns @ RL = 5
-3
• Operating temperature range
– From –30°C to +85°C
WT
– From –40°C to +105°C
AT
• Revision
:A
Note:
1. For Fast
t
RCD/
t
RP, contact factory.
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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