EEWORLDEEWORLDEEWORLD

Part Number

Search

510BAA-AAAG

Description
osc prog 3.3V lvds 50ppm 5x7mm
CategoryPassive components   
File Size1MB,26 Pages
ManufacturerSilicon
Environmental Compliance  
Download Datasheet View All

510BAA-AAAG Overview

osc prog 3.3V lvds 50ppm 5x7mm

S i 5 1 0 / 5 11
C
R YS TA L
O
SCILLATOR
(XO) 100 kH
Z
Features
TO
250 MH
Z
Supports any frequency from
100 kHz to 250 MHz
Low jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5 x 7 and
3.2 x 5 mm packages
Pb-free, RoHS compliant
–40
to 85
o
C operation
Si5602
Applications
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
Ordering Information:
See page 14.
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
FPGA/ASIC clock generation
Pin Assignments:
See page 12.
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
OE
1
4
V
DD
GND
2
3
CLK
Si510 (CMOS)
NC
OE
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Functional Block Diagram
V
DD
OE
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
OE
OE
1
1
2
2
3
3
6
6
5
5
4
4
V
DD
V
DD
CLK–
CLK–
CLK+
CLK+
Low Noise Regulator
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
DSPLL
®
Synthesis
CLK+
CLK–
NC
NC
GND
GND
GND
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
Rev. 1.2 7/15
Copyright © 2015 by Silicon Laboratories
Si510/511
RISC-V SoC FPGA architecture brings real-time performance to Linux
Microchip, through its Microsemi Corporation subsidiary, has announced the expansion of its Mi-V ecosystem with the launch of a new SoC FPGA architecture that combines the lowest power mid-range Polar...
朗锐智科 Linux and Android
How to read HCS12 paging area constants?
[font=Times New Roman][size=4][color=blue]Hardware platform: MC9S12HY64 Development environment: CODEWARRIOR V5.0 Compilation mode is BANK mode, the code is as follows: const UINT8 __far fardata @0xe8...
liufan NXP MCU
If you develop a private application based on a ZigBee Mesh network, which protocol stack should you choose?
[align=left][color=#000]Many users just want to use the functions of ZigBee mesh network in their own systems or products, and do not need to follow the application layer specifications defined by Zig...
john_wang RF/Wirelessly
avr mega16 photoelectric encoder distance measurement
This is my first time to use this thing. I hope you can give me a source code for reference. Thank you....
f1342665636 Microchip MCU
Download address of Guo Tianxiang's video tutorial on learning C51 microcontroller in ten days, which is recognized as the best in China
Guo Tianxiang learned C51 microcontroller video tutorial in ten days It is currently recognized as the best video tutorial in the country. It is easy to understand and easy to use, very suitable for b...
tyxdz 51mcu
Simple VHDL syntax problem
I defined SRAM_DATA1: inout std_logic_vector(15 downto 0); r: std_logic_vector(7 downto 0) to assign the first eight bits of SRAM_DATA1 to r. How do I write it in VHDL format? I need code....
kfchu Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 198  2452  35  78  1596  4  50  1  2  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号