Default Frequency and VCXO Pull Range
Order Information for Ceramic 5x7 Devices
ORDERING INFORMATION
Ordering Information for FemtoClock
®
NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a variety of
devices options such as the output type, number of default frequen-
cies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequencies and VCXO pull range must be specified at the
time of order and are programmed by IDT before the shipment. Table
1 specifies the available order codes including the device options.
Table 2 to table 4 specify the default frequency configurations.
Example part number: order code 8N3QV01FD-0001CDI specifies a
programmable, quad default-frequency VCXO with a voltage supply
of 2.5V, a LVPECL output, a
50
ppm crystal frequency accuracy,
contains a 114.285MHz internal crystal as frequency source,
industrial temperature range, a lead-free (6/6 RoHS) 10-lead ceramic
5mm x 7mm x 1.55mm package and is factory-programmed to the
default frequencies of 100, 122.88, 125 and 156.25MHz and to the
VCXO pull range of min.
100
ppm. The default frequency
configuration is found in table 1.
Other default frequencies and order codes are available from IDT on
request.
Look up default frequencies from tables 2, 3 and 4 by using the
left-most frequency column for single-frequency devices, the two
left-most columns for dual and all four columns for quad-frequency
devices, respectively.
Table 1. Order Codes
8N X
X
XXX X X - dddd XX X
X
Shipping Package
8:
Tape & Reel
(no letter): Tray
Ambient Temperature Range
“I”: Industrial: (T
A
= -40°C to 85°C)
(no letter) : (T
A
= 0°C to 70°C)
Package Code
CD:
Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Number of Default Frequencies
S:
1: Single
D:
2: Dual
Q:
4: Quad
Default-Frequency and VCXO Pull Range
See
document
FemtoClock NG Ceramic-Package XO and VCXO
Ordering Product Information.
dddd
Part Number
Function #Pins
001
003
V01
V03
V75
V76
V85
085
270
271
272
273
XO
XO
VCXO
VCXO
VCXO
VCXO
VCXO
XO
XO
XO
XO
XO
10
10
10
10
6
6
6
6
6
6
6
6
OE fct. at
pin
OE@2
OE@1
OE@2
OE@1
OE@2
nOE@2
—
OE@1
OE@1
OE@2
nOE@2
nOE@1
Die Revision
G
Option Code (Supply Voltage and Frequency-Stability)
A:
V
CC
= 3.3V±5%, ±100ppm
B:
V
CC
= 2.5V±5%, ±100ppm
E:
V
CC
= 3.3V±5%, ±50ppm
F:
V
CC
= 2.5V±5%, ±50ppm
K:
V
CC
= 3.3V±5%, ±20ppm
L:
V
CC
= 2.5V±5%, ±20ppm
Last digit =
L:
configuration pre-programmed and not changable
0000
to
0999
1000
to
1999
2000
to
2999
f
XTAL
(MHz)
114.285
100.000
PLL feedback
Fractional
Integer
Fractional
Use for
VCXO, XO
XO
XO
Table
2
3
4
FemtoClock NG
I/O Identifier
0:
LVCMOS
3:
LVPECL
4:
LVDS
REVISION 24 MARCH 28, 2012
1
©2012 Integrated Device Technology, Inc.
Ordering Information
Default Frequency and VCXO Pull Range Order Information for Ceramic 5x7 Devices
Table 2. Default Frequencies and Ordering Information for f
XTAL
=114.285MHz
Code (dddd)
Single Frequency
Devices
Dual Frequency Devices
FSEL=0
FSEL=1
Quad Frequency Devices
FSEL[1:0]=01
400
231.25
312.5
400
156.25
322.265625
40.5
50
83.33
121.109
100.011
166.62875
156.25
155.52
212
98
135
312.5
110
95
99
74.174
148.35
106.25
FSEL[1:0]=10
1000
231.25
175
1000
212.5
125
67.5
50
100
121.109
99.989
166.62875
212.5
155.52
212
102
270
125
125
105
102
74.25
148.5
125
FSEL[1:0]=11
1000
231.25
156.25
250
150
265.625
135
50
83.33
121.109
100.022
166.62875
106.25
155.52
212
99
108
250
130
125
100
74.174
148.35
300
Default Frequencies (MHz)
Pull range (ppm)
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
FSEL[1:0]=00
100
231.25
350
100
150
328.125
100
50
100
121.109
100
166.62875
100
155.52
212
100
81
156.25
100
100
98
74.25
148.5
100
±100
±100
±100
±100
±100
±100
±100
±100
±100
±100
±100
±100
±75
±137.5
±100
±100
±100
±100
±100
±100
±100
±100
±100
NOTE: Other default frequencies can be obtained from IDT on request.
NOTE: Pull range is only applicable to VCXO devices. When ordering a XO device, the pull range can be ignored.
NOTE: Default pull range is: ±100ppm.
REVISION 24 MARCH 28, 2012
5
©2012 Integrated Device Technology, Inc.
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
