Freescale Semiconductor
Technical Data
Document Number: MC33975
Rev 11.0, 01/2014
Multiple Switch Detection
Interface with Suppressed
Wake-up and 32 mA Wetting
Current
The 33975 Multiple Switch Detection Interface with Suppressed Wake-
up is designed to detect the closing and opening of up to 22 switch
contacts. The switch status, either open or closed, is transferred to the
microprocessor unit (MCU) through a serial peripheral interface (SPI).
The device also features a 22-to-1 analog multiplexer for reading
inputs as analog.
The 33975 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors the switch
change of state. The Sleep mode provides low quiescent current,
which makes the 33975 ideal for automotive and industrial products
requiring low sleep state currents.
Improvements are a programmable interrupt timer for Sleep mode that
can be disabled, switch detection currents of 32 mA and 4.0 mA for
switch-to-ground inputs, and an interrupt bit that can be reset. This
device is powered using SMARTMOS technology.
Features
•
•
•
•
•
•
•
Designed to operate from 5.5 V
V
PWR
28 V
Switch input voltage: (33975: -14 to 38 V) (33975A: -14 to 40 V)
Interfaces to microprocessor using 3.3 V/5.0 V SPI protocol
Selectable wake-up on change of state
14 switch-to-ground inputs
8 programmable inputs (switches to battery or ground)
Selectable wetting current (32 mA or 4.0 mA for switch-to-ground
inputs)
• Sleep State current V
PWR
100
A,
V
DD
20
A
33975
33975A
MULTIPLE SWITCH
DETECTION INTERFACE WITH
SUPPRESSED WAKE-UP
EK SUFFIX (PB-FREE)
98ASA10556D
32-PIN SOICW EP
Applications
• Automotive systems
• Industrial control systems
• Process control systems
• Security systems
• Systems requiring switch status verification for
safety, operation, or process control purposes
VDD
V
BAT
SP0
SP1
V
BAT
SP7
SG0
SG1
SI
SCLK
CS
SO
INT
AMUX
GND
V
BAT
POWER SUPPLY
LVI
33975
VPWR
VDD
WAKE
VDD
ENABLE
SG12
SG13
MOSI
SCLK
CS
MISO
INT
AN0
MCU
WATCHDOG
RESET
Figure 1. 33975 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2005 - 2014. All rights reserved.
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number
MC33975TEK/R2
MC33975ATEK/R2
Temperature (T
A
)
-40 to 125 °C
Package
32 SOICW-EP
Switch Input Voltage Range
-14 to 38 V
DC
-14 to 40 V
DC
Reference Location
5
5
33975
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V
V
PWR
V
PWR
32.0
mA
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
16.0
mA
To
+
2.0 4.0 V
‚
SPI
mA Ref
Comparator
5.0 V
V
PWR
5.0 V
To
+
4.0 V
‚
SPI
Ref
Comparator
WAKE
WAKE
Control
SP0
V
PWR
V
PWR
, V
DD
, 5.0V
POR
Bandgap
Sleep PWR
4.0
mA
VPWR
VDD
GND
16.0
mA
To
+
2.0 4.0 V
‚
SPI
mA Ref
Comparator
V
PWR
V
PWR
32.0
mA
4.0
mA
SP7
5.0 V
Oscillator
and
Clock Control
V
PWR
5.0 V
Temperature
Monitor and
Control
5.0 V
125 k
V
PWR
V
PWR
32.0
mA
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
V
PWR
V
PWR
32.0
mA
4.0
mA
4.0
mA
SG0
SPI Interface
and Control
V
DD
125 k
INT
INT
Control
VDD
MUX Interface
40
A
CS
V
DD
SCLK
SI
SO
SG13
To
+
4.0 V
‚
SPI
Ref
Comparator
+
V
DD
Analog Mux
Output
‚
AMUX
Figure 2. 33975 Simplified Internal Block Diagram
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
GND
SI
SCLK
CS
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SO
VDD
AMUX
INT
SP7
SP6
SP5
SP4
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
Figure 3. 33975 Pin Connections
Table 2. Pin Definitions
A functional description of each Pin can be found in the Functional Pin Description section on page
12.
Pin
1
2
3
4
5–8
25–28
9–15,
18–24
16
17
29
30
31
32
Pin Name
GND
SI
SCLK
CS
SPn
SGn
VPWR
WAKE
INT
AMUX
VDD
SO
Formal Name
Ground
SPI Slave In
Serial Clock
Chip Select
Programmable Switches 0–3
Programmable Switches 4–7
Switch-to-Ground Inputs 0–6
Switch-to-Ground Inputs 13–7
Battery Input
Wake-up
Interrupt
Analog Multiplex Output
Voltage Drain Supply
SPI Slave Out
Description
Ground for logic, analog, and switch-to-battery inputs
SPI control data input pin from MCU to 33975
SPI control clock input pin
SPI control chip select input pin from MCU to 33975. Logic [0] allows data to be
transferred in
Programmable switch-to-battery or switch-to-ground input pins
Switch-to-ground input pins
Battery supply input pin. This pin requires external reverse battery protection.
Open drain wake-up output is designed to control a power supply enable pin
Open-drain output to MCU is used to indicate input switch change of state
Analog multiplex output
3.3/5.0 V supply sets SPI communication level for the SO driver
Provides digital data from 33975 to the MCU
33975
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent
damage to the device.
Rating
ELECTRICAL RATINGS
VDD Supply Voltage
CS, SI, SO, SCLK, INT, AMUX
WAKE
VPWR Supply Voltage
VPWR Supply Voltage at -40
C
Switch Input Voltage Range
33975
33975A
Frequency of SPI Operation (V
DD
= 5.0 V)
ESD Voltage
(1)
Human Body
Model
(2)
V
ESD
±2000
±2000
±200
750
500
Applies to all non-input Pins
Machine Model
Charge Device Model
Corner Pins
Interior Pins
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Case
Storage Temperature
Power Dissipation
(3)
T
A
T
J
T
C
T
STG
P
D
-40 to 125
-40 to 150
-40 to 125
-55 to 150
1.7
–
–
–
–
–
–
–
-14 to 38
-14 to 40
6.0
MHz
V
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
-0.3 to 50
-0.3 to 45
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
Symbol
Value
Unit
C
C
W
Notes
1. ESD testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
),
the Machine Model (C
ZAP
=
200 pF, R
ZAP
= 0
),
and the Charge Device Model.
2.
3.
4.
All Programmable Switches (SP) and Switch-to-Ground (SG) input pins when tested individually.
Maximum power dissipation at T
J
=150
C junction temperature with no heatsink used.
Thermal resistance between the die and the exposed die pad.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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