S6E1A12B0AGN20000 datasheet, PDF

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S6E1A12B0AGN20000: DescriptionIC mcu 32bit 88 K flash 32-qfn; Categorysemiconductor The embedded processor and controller; File Size2MB，96 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

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IC mcu 32bit 88 K flash 32-qfn

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S6E1A Series

32-bit ARM

Cortex

-M0+

FM0+ Microcontroller

The S6E1A Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power

consumption and low cost.

This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such

as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN).

The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL

MANUAL".

Features

32-bit ARM Cortex-M0+ Core



Processor version: r0p1



Maximum operating frequency: 40 MHz



Nested Vectored Interrupt Controller (NVIC): 1 NMI

(non-maskable interrupt) and 32 peripheral interrupt with 4

selectable interrupt priority levels



CSIO



Full

duplex double buffer

dedicated baud rate generator



Overrun error detection function



Serial chip select function (ch.1 and ch.3 only)



Data length: 5 to 16 bits



Built-in



LIN

protocol Rev.2.1 supported



Full duplex double buffer



Master/Slave mode supported



LIN break field generation function (The length is variable

between 13 bits and 16 bits.)



LIN break delimiter generation function (The length is

variable between 1 bit and 4 bits.)



Various error detection functions available (parity errors,

framing errors, and overrun errors)



LIN



24-bit System timer (Sys Tick): System timer for OS task

management

Bit Band operation

Compatible with Cortex-M3 bit band operation

On-Chip Memories



Flash memory

to 88 Kbyte



Read cycle:0 wait-cycle



Security function for code protection







Standard-mode

(Max: 100 kbps) supported / Fast-mode

(Max 400kbps) supported.



SRAM

The on-chip SRAM of this series has one independent SRAM.



SRAM: 6 Kbyte

Multi-function Serial Interface (Max 3channels)



128 bytes with FIFO in all channels (The number of FIFO

steps varies depending on the settings of the communication

mode or bit length.)



The operation mode of each channel can be selected from

one of the following.



UART



CSIO



LIN





UART

duplex double buffer



Parity can be enabled or disabled.



Built-in dedicated baud rate generator



External clock available as a serial clock



Full



Various error detection functions (parity errors, framing errors,

and overrun errors)

Cypress Semiconductor Corporation

Document Number: 002-05091 Rev.*B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised April 13, 2017

S6E1A Series

Contents

1. Product Lineup .................................................................................................................................................................. 6

2. Packages ........................................................................................................................................................................... 7

3. Pin Assignment ................................................................................................................................................................. 8

4. Pin Descriptions .............................................................................................................................................................. 13

5. I/O Circuit Type................................................................................................................................................................ 24

6. Handling Precautions ..................................................................................................................................................... 29

6.1

Precautions for Product Design ................................................................................................................................... 29

6.2

Precautions for Package Mounting .............................................................................................................................. 30

6.3

Precautions for Use Environment ................................................................................................................................ 32

7. Handling Devices ............................................................................................................................................................ 33

8. Block Diagram ................................................................................................................................................................. 36

9. Memory Size .................................................................................................................................................................... 37

10. Memory Map .................................................................................................................................................................... 37

11. Pin Status in Each CPU State ........................................................................................................................................ 40

12. Electrical Characteristics ............................................................................................................................................... 44

12.1 Absolute Maximum Ratings ......................................................................................................................................... 44

12.2 Recommended Operating Conditions.......................................................................................................................... 45

12.3 DC Characteristics....................................................................................................................................................... 46

12.3.1 Current Rating .............................................................................................................................................................. 46

12.3.2 Pin Characteristics ....................................................................................................................................................... 49

12.4 AC Characteristics ....................................................................................................................................................... 50

12.4.1 Main Clock Input Characteristics .................................................................................................................................. 50

12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 51

12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 52

12.4.4 Operating Conditions of Main PLL (In the case of using the main clock as the input clock of the PLL) ....................... 53

12.4.5 Operating Conditions of Main PLL

(In the case of using the built-in high-speed CR clock as the input clock of the main PLL).......................................... 53

12.4.6 Reset Input Characteristics .......................................................................................................................................... 54

12.4.7 Power-on Reset Timing................................................................................................................................................ 54

12.4.8 Base Timer Input Timing .............................................................................................................................................. 55

12.4.9 CSIO/UART Timing ...................................................................................................................................................... 56

12.4.10 External Input Timing ................................................................................................................................................ 72

12.4.11 QPRC Timing ........................................................................................................................................................... 73

12.4.12 I

C Timing ................................................................................................................................................................. 75

12.4.13 SW-DP Timing .......................................................................................................................................................... 76

12.5 12-bit A/D Converter .................................................................................................................................................... 77

12.6 Low-voltage Detection Characteristics ........................................................................................................................ 80

12.6.1 Low-voltage Detection Reset ....................................................................................................................................... 80

12.6.2 Low-voltage Detection Interrupt ................................................................................................................................... 81

12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 82

12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 83

12.8.1 Return Factor: Interrupt ................................................................................................................................................ 83

12.8.2 Return Factor: Reset .................................................................................................................................................... 85

13. Ordering Information ...................................................................................................................................................... 87

14. Package Dimensions ...................................................................................................................................................... 88

15. Major Changes ................................................................................................................................................................ 93

Document Number: 002-05091 Rev.*B

Page 4 of 96

S6E1A12B0AGN20000 Related Products

	S6E1A12B0AGN20000	S6E1A12B0AGP20000	S6E1A12C0AGV20000
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