PDIUSBD12 datasheet, PDF - EEWORLD Datasheet

PDIUSBD12

USB interface device with parallel bus

Rev. 08 — 20 December 2001

Product data

1. Description

The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in

microcontroller based systems and communicates with the system microcontroller

over the high-speed general purpose parallel interface. It also supports local DMA

transfer.

This modular approach to implementing a USB interface allows the designer to

choose the optimum system microcontroller from the available wide variety. This

ﬂexibility cuts down the development time, risks, and costs by allowing the use of the

existing architecture and minimize ﬁrmware investments. This results in the fastest

way to develop the most cost effective USB peripheral solution.

The PDIUSBD12 fully conforms to the

USB speciﬁcation Rev. 2.0 (basic speed).

It is

also designed to be compliant with most device class speciﬁcations: Imaging Class,

Mass Storage Devices, Communication Devices, Printing Devices, and Human

Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like

Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers

an immediate cost reduction for applications that currently use SCSI

implementations.

The PDIUSBD12 low suspend power consumption along with the LazyClock output

allows for easy implementation of equipment that is compliant to the ACPI™,

OnNOW™, and USB power management requirements. The low operating power

allows the implementation of bus powered peripherals.

In addition, it also incorporates features like SoftConnect™, GoodLink™,

programmable clock output, low frequency crystal oscillator, and integration of

termination resistors. All of these features contribute to signiﬁcant cost savings in the

system implementation and at the same time ease the implementation of advanced

USB functionality into the peripherals.

2. Features

s

Complies with the

Universal Serial Bus speciﬁcation Rev. 2.0 (basic speed)

s

High performance USB interface device with integrated SIE, FIFO memory,

transceiver and voltage regulator

s

Compliant with most Device Class speciﬁcations

s

High-speed (2 Mbytes/s) parallel interface to any external microcontroller or

microprocessor

s

Fully autonomous DMA operation

s

Integrated 320 bytes of multi-conﬁguration FIFO memory

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

s

Double buffering scheme for main endpoint increases throughput and eases

real-time data transfer

s

Data transfer rates: 1 Mbytes/s achievable in Bulk mode, 1 Mbits/s achievable in

Isochronous mode

s

Bus-powered capability with very good EMI performance

s

Controllable LazyClock output during suspend

s

Software controllable connection to the USB bus (SoftConnect™)

s

Good USB connection indicator that blinks with trafﬁc (GoodLink™)

s

Programmable clock frequency output

s

Complies with the ACPI, OnNOW and USB power management requirements

s

Internal Power-on reset and low-voltage reset circuit

s

Available in SO28 and TSSOP28 pin packages

s

Full industrial grade operation from

−40

to +85

°C

s

Higher than 8 kV in-circuit ESD protection lowers cost of extra components

s

Full-scan design with high fault coverage (>99%) ensures high quality

s

Operation with dual voltages:

3.3

±0.3

V or extended 5 V supply range of 4.0 to 5.5 V

s

Multiple interrupt modes to facilitate both bulk and isochronous transfers.

3. Pinning information

3.1 Pinning

Fig 1. Pin conﬁguration.

9397 750 09238

Product data

Rev. 08 — 20 December 2001

2 of 35

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

3.2 Pin description

Table 1:

Symbol

DATA <0>

DATA <1>

DATA <2>

DATA <3>

GND

DATA <4>

DATA <5>

DATA <6>

DATA <7>

ALE

Pin description

1

2

3

4

5

6

7

8

9

10

Type

[1]

IO2

P

IO2

I

Description

Bit 0 of bidirectional data. Slew-rate controlled.

Bit 1 of bidirectional data. Slew-rate controlled.

Bit 2 of bidirectional data. Slew-rate controlled.

Bit 3 of bidirectional data. Slew-rate controlled.

Ground.

Bit 4 of bidirectional data. Slew-rate controlled.

Bit 5 of bidirectional data. Slew-rate controlled.

Bit 6 of bidirectional data. Slew-rate controlled.

Bit 7 of bidirectional data. Slew-rate controlled.

Address Latch Enable. The falling edge is used to close the

latch of the address information in a multiplexed address/ data

bus. Permanently tied LOW for separate address/ data bus

conﬁguration.

Chip Select (Active LOW).

Device is in Suspend state.

Programmable Output Clock (slew-rate controlled).

Interrupt (Active LOW).

Read Strobe (Active LOW).

Write Strobe (Active LOW).

DMA Request.

DMA Acknowledge (Active LOW).

End of DMA Transfer (Active LOW). Double up as V

BUS

sensing.

EOT_N is only valid when asserted together with DMACK_N

and either RD_N or WR_N.

Reset (Active LOW and asynchronous). Built-in Power-on reset

circuit present on chip, so pin can be tied HIGH to V

CC

.

GoodLink LED indicator (Active LOW)

Crystal Connection 1 (6 MHz).

Crystal Connection 2 (6 MHz). If external clock signal, instead

of crystal, is connected to XTAL1, then XTAL2 should be

ﬂoated.

Voltage supply (4.0

−

5.5 V).

To operate the IC at 3.3 V, supply 3.3 V to both V

CC

and V

OUT3.3

pins.

USB D− data line.

USB D+ data line.

CS_N

CLKOUT

INT_N

RD_N

WR_N

DMREQ

EOT_N

11

13

14

15

16

17

19

I

I,OD4

O2

OD4

I

O4

I

SUSPEND 12

DMACK_N 18

RESET_N

GL_N

XTAL1

XTAL2

20

21

22

23

I

OD8

I

O

V

CC

24

P

D−

D+

25

26

A

9397 750 09238

Product data

Rev. 08 — 20 December 2001

3 of 35

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

Pin description

…continued

27

28

Type

[1]

P

I

Description

3.3 V regulated output. To operate the IC at 3.3 V, supply a

3.3 V to both V

CC

and V

OUT3.3

pins.

Address bit. A0 = 1 selects command instruction; A0 = 0 selects

the data phase. This bit is a don’t care in a multiplexed address

and data bus conﬁguration and should be tied HIGH.

Table 1:

Symbol

V

OUT3.3

A0

[1]

O2 : Output with 2 mA drive

OD4: Output Open Drain with 4 mA drive

OD8: Output Open Drain with 8 mA drive

IO2: Input and Output with 2 mA drive

O4 : Output with 4 mA drive.

4. Ordering information

Table 2:

Packages

28-pin plastic SO

28-pin plastic TSSOP

Ordering information

Temperature range

−40 °C

to +85

°C

−40 °C

to +85

°C

Outside North America

PDIUSBD12 D

PDIUSBD12 PW

North America

PDIUSBD12 D

PDIUSBD12PW DH

Pkg. Dwg. #

SOT136-1

SOT361-1

5. Block diagram

This is a conceptual block diagram and does not include each individual signal.

Fig 2. Block diagram.

9397 750 09238

Product data

Rev. 08 — 20 December 2001

4 of 35

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

6. Functional description

6.1 Analog transceiver

The integrated transceiver interfaces directly to the USB cables through termination

resistors.

6.2 Voltage regulator

A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage

is also provided as an output to connect to the external 1.5 kΩ pull-up resistor.

Alternatively, the PDIUSBD12 provides SoftConnect technology with an integrated

1.5 kΩ pull-up resistor.

6.3 PLL

A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip.

This allows for the use of a low-cost 6 MHz crystal. EMI is also minimized due to the

lower frequency crystal. No external components are needed for the operation of the

PLL.

6.4 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

using 4× oversampling principle. It is able to track jitter and frequency drift speciﬁed

by the USB speciﬁcation.

6.5 Philips Serial Interface Engine (PSIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization pattern recognition, parallel/serial conversion, bit stufﬁng/de-stufﬁng,

CRC checking/generation, PID veriﬁcation/generation, address recognition, and

handshake evaluation/generation.

6.6 SoftConnect

The connection to the USB is accomplished by bringing D+ (for high-speed USB

device) HIGH through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up

resistor is integrated on-chip and is not connected to V

CC

by default. The connection

is established through a command sent by the external/system microcontroller. This

allows the system microcontroller to complete its initialization sequence before

deciding to establish connection to the USB. Re-initialization of the USB bus

connection can also be performed without requiring to pull out the cable.

The PDIUSBD12 will check for USB V

BUS

availability before the connection can be

established. V

BUS

sensing is provided through pin EOT_N. See

Section 3.2 “Pin

description”

for details. Sharing of V

BUS

sensing and EOT_N can be easily

accomplished by using V

BUS

voltage as the pull-up voltage for the normally

open-drain output of the DMA controller pin.

9397 750 09238

Product data

Rev. 08 — 20 December 2001

5 of 35

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