ZLF645E0Q2064G datasheet, PDF - EEWORLD Datasheet

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ZLF645E0Q2064G: Description8-BIT, FLASH, 8MHz, MICROCONTROLLER, QCC20, GREEN, QFN-20; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，202 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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ZLF645E0Q2064G Overview

8-BIT, FLASH, 8MHz, MICROCONTROLLER, QCC20, GREEN, QFN-20

ZLF645E0Q2064G Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1358925495
Parts packaging code	QFN
package instruction	GREEN, QFN-20
Contacts	20
Reach Compliance Code	unknown
Has ADC	NO
Address bus width
bit size	8
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-XQCC-N20
length	5 mm
Humidity sensitivity level	NOT SPECIFIED
Number of I/O lines	16
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
ROM programmability	FLASH
Maximum seat height	1 mm
speed	8 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	1.9 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	NOT SPECIFIED
Terminal form	NO LEAD
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ZLF645 Series Flash MCUs

Product Specification

Table of Contents

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comparator Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comparator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 0/1 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 3 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 4 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flash Program/Constant Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Linear Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stack Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

19-4572; Rev 0; 4/09able

of ContentsTable able of

Table

Table of Contents

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