TC4 TCXO SERIES
n
THRU-HOLE OR SURFACE MOUNT TCXO IN METAL PACKAGE
STANDARD SPECIFICATIONS:
Frequency Range
Operating Temperature Range
vs. Temperature
Frequency Stability
vs. Supply Voltage
Aging
Frequency Adjustment by Trimmer
Input Voltage
Output Logic
Output Voltage Levels
Input Current (Icc) or Current Consumption
Output Load
Packaging
10.00 MHz - 60.00 MHz (Consult factory for specific available frequencies)
Various temperature ranges up to -40 to +85°C available.
±
1.5, 2, 2.5, 3, 5, and 10 PPM over the operating temperature range
available. See below for available frequency stability options per
temperature range.
±
0.5 PPM maximum over 5V
±
5%
3 PPM first year, 1 PPM per year thereafter at 25°C
±
5°C
±
3 PPM minimum
5
±
5% Volt standard, but 3.3 V also available for HCMOS output
HCMOS
Clipped Sine Wave (5V)
Logic 0: 0.5 V max.,
1 Vp-p min.
Logic 1: 4.5 V min.
20 - 40 mA max.
2 - 5 mA max.
10 TTL + 15 pF
10kΩ/10 Pf
TC46 & 47: 20 parts per tube, TC48: TBD
PART NUMBERING GUIDE:
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The Pletronics part number for a TC4 series TCXO consists of the following 6 elements:
1. Model Number (Voltage):
2. Package:
TC4
= 5V
TC46: Thru-Hole, 4.7 mm High
3TC4 = 3.3V
TC47: Surface Mount, 5.5 mm High
TC48: Surface Mount, 4.0 mm High
3.
Logic:
4. Frequency Stability:
TC46C: Clipped Sine Wave (5V only)
TC46C015:
±1.5
PPM
TC46H: HCMOS (5V or 3.3V)
TC46C020:
±2
PPM
TC46C025:
±2.5
PPM
TC46C030:
±3
PPM
TC46C050:
±5
PPM
TC46C100:
±10
PPM
5.
Operating Temperature Range {with Tightest Frequency Stability Available}:
TC46C015A: 0 to +50°C
{± 1.5 PPM}
TC46C015B: 0 to +70°C
{± 1.5 PPM}
TC46C020C: -10 to +70°C
{± 2.0 PPM}
TC46C020D: -20 to +75°C
{± 2.0 PPM}
TC46C025E: -30 to +75°C
{± 2.5 PPM}
TC46C050F: -40 to +85°C
{± 5.0 PPM}
Frequency of Operation in MHz
6.
EXAMPLE: TC46C025A-12.800 MHz, 3TC48H050D-10.000 MHz, TC47C050F-40.000 MHz
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When customer’s requirements are non-standard, a special engineering part number will be assigned.
(continued)
Telephone: (425) 776-1880, Fax: (425) 776-2760, e-mail: ple-sales@pletronics.com
T6A
TC4 TCXO SERIES
Recommended Test Circuit for TC46 & 47
Recommended Test Circuit for TC48
*CL (Capacitive Load): Includes the input capacitance of oscilloscope.
**Add a 20K resistor from output to gnd for Clipped Sine Wave version only (not needed for HCMOS version)
TC4 PACKAGE OUTLINES (NOT TO SCALE)
PACKAGE 6
TRIMMER HOLE FOR FREQUENCY ADJUSTMENT (LOCATION MAY VARY)
0
4
PACKAGE 7
0.72
(18.4±0.2)
0.04 (1.0)
0.47
(12.0±0.5)
.
0.46
(11.7)
0.16 (4.0)
0.73
(18.5± 0.5)
0.84
(21.3±0.3)
0.185
(4.7 + 0.2)
0.20
(5.0 MIN)
0.16
0
0.100
(2.5±0.2)
(4±0.1)
0.16 (4.0)
0.04 (1.0)
1
0.16
(4.0)
0.22
(5.5)
0.16
(4.0)
0.07
(1.78)
0.150
(3.81)
0.30
(7.62)
7
0.30
(7.5±0.3)
1
7
14
0.590
(15±0.4)
8
0.17 (4.32)
0.04
(1.01)
0.66
(16.76)
LAND PATTERN
14
0.60
8
(15.0±0.5)
PACKAGE 8
PIN CONNECTIONS
0.46
(11.6)
0.38
(9.6 ±0.2)
GND
0.45
(11.4 ±0.2)
GND
.36 (9.14)
.055
(1.4)
.110
(2.79)
.10 (2.5)
PIN
1
OUTPUT
GND
N.C.
Vcc
CONNECTION
No Connection
GROUND & CASE
OUTPUT
Vcc
0.100
(2.54)
0.100
(2.54)
0.100
(2.54)
7
8
14
0.04 (1.0)
INCHES (MILLIMETERS)
LAND
PATTERN
0.100
(2.5 ±0.3)
0.12
(3.0 ±0.2)
0.15
(3.9 MAX)
.100
(2.54)
TYP
October 2000
T6B
Pletronics Inc., 19013 36
th
Ave. W., Suite H, Lynnwood, WA 98036-5761 USA
FPGA/CPLD
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