EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

1812Y5000332JCB

Description
Ceramic Capacitor, Multilayer, Ceramic, 500V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0033uF, Surface Mount, 1812, CHIP
CategoryPassive components    capacitor   
File Size2MB,9 Pages
ManufacturerKnowles
Websitehttp://www.knowles.com
Environmental Compliance
Download Datasheet Parametric View All

1812Y5000332JCB Overview

Ceramic Capacitor, Multilayer, Ceramic, 500V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0033uF, Surface Mount, 1812, CHIP

1812Y5000332JCB Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid2091670789
package instruction, 1812
Reach Compliance Codecompliant
Country Of OriginMainland China
ECCN codeEAR99
YTEOL7.69
capacitance0.0033 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high3.2 mm
JESD-609 codee3
length4.5 mm
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance5%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package formSMT
method of packingBulk
positive tolerance5%
Rated (DC) voltage (URdc)500 V
size code1812
surface mountYES
Temperature characteristic codeC0G
Temperature Coefficient30ppm/Cel ppm/°C
Terminal surfaceMatte Tin (Sn) - with Nickel (Ni) barrier
Terminal shapeWRAPAROUND
width3.2 mm
How to communicate between USART and PC
/********************************************************************************\File name: main.cDescription; For MSP430F149.Asynchronous communication.Version: 4.20.1 sun_seven\********************...
nillht Microcontroller MCU
Design of stopwatch based on FPGA
I just finished the course design, and I'd like to share a stopwatch program. The experimental version is Altera's EP2C5Q208C8, with a 50MHz crystal. The functions are reset, start and stop, and the d...
yz416154664 FPGA/CPLD
The CORDIC algorithm is designed based on the FPGA signal generator.
I am making a program to generate sine waves using the CORDIC algorithm. It is written in Q2, but modelsim can simulate the sine wave waveform, but the waveform captured by signaltap is reversed. I ca...
liucome199 FPGA/CPLD
New OBD device with intelligent brake light control system
The intelligent brake light control system is a vehicle active safety technology based on visual perception. Through visual enhancement and visual information transmission, it compares and tests vario...
xiongyu0 Automotive Electronics
Wince data abort problem seeking ideas
Double-click the directory, and then the following situation appears Data Abort: Thread=83cfe400 Proc=821267c0 'explorer.exe' AKY=00000011 PC=03fb8cd8(coredll.dll+0x00048cd8) RA=03e81f04(commctrl.dll+...
haxinglong Embedded System
My idea is very simple. I just want to make a hardware management framework independent of the microcontroller.
Maybe as you listen, you will gradually find that what I am talking about sounds more and more like a microcontroller real-time operating system - but I just want to say, don't scare me. I don't have ...
辛昕 Programming Basics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1590  1178  984  2060  1975  33  24  20  42  40 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号