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GTLP10B320MTDX_NL

Description
Registered Bus Transceiver, GTLP Series, 1-Func, 10-Bit, True Output, BICMOS, PDSO56, 6.10 MM, MO-153, TSSOP-56
Categorylogic    logic   
File Size259KB,12 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric View All

GTLP10B320MTDX_NL Overview

Registered Bus Transceiver, GTLP Series, 1-Func, 10-Bit, True Output, BICMOS, PDSO56, 6.10 MM, MO-153, TSSOP-56

GTLP10B320MTDX_NL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instruction6.10 MM, MO-153, TSSOP-56
Contacts56
Reach Compliance Codecompliant
Control typeCOMMON CONTROL
Counting directionBIDIRECTIONAL
seriesGTLP
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
MaximumI(ol)0.05 A
Humidity sensitivity level2
Number of digits10
Number of functions1
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Maximum supply current (ICC)45 mA
Prop。Delay @ Nom-Sup7.5 ns
propagation delay (tpd)10 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
translateGTLP & LVTTL
Trigger typePOSITIVE EDGE
width6.1 mm
Base Number Matches1
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
May 2001
Revised May 2001
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and
receiver, with separate LVTTL inputs and outputs and a
feedback path for diagnostics, that provides LVTTL to
GTLP signal level translation. High speed backplane oper-
ation is a direct result of GTLP’s reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the
Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output low level is typ-
ically less than 0.5V, the output level high is 1.5V and the
receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Variable edge rate control pin to select desired edge rate
on GTLP port (V
ERC
)
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Split LVTTL inputs and outputs
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
A feedback path for control and diagnostics monitoring
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP10B320MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500483
www.fairchildsemi.com
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