BUSY and LDAC Functions...................................................... 35
REVISION HISTORY
10/04: Data Sheet Changed from Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 7
Changes to Figure 36...................................................................... 35
Changes to Figure 37...................................................................... 36
Changes to Figure 38...................................................................... 36
Changes to Ordering Guide .......................................................... 41
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 44
AD5390/AD5391/AD5392
GENERAL DESCRIPTION
The AD5390/AD5391 are complete single-supply, 16-channel,
14-bit and 12-bit DACs, respectively. The AD5392 is a complete
single-supply, 8-channel, 14-bit DAC. Devices are available both
in 64-lead LFCSP and 52-lead LQFP packages. All channels
have an on-chip output amplifier with rail-to-rail operation. All
devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an
on-chip channel monitor function that multiplexes the analog
outputs to a common MON_OUT pin for external monitoring,
and an output amplifier boost mode that optimizes the output
amplifier slew rate.
The AD5390/AD5391/AD5392 contain a 3-wire serial interface
with interface speeds in excess of 30 MHz that are compatible
Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Model
AD5380BST-5
AD5380BST-3
AD5384BBC-5
AD5384BBC-3
AD5381BST-5
AD5381BST-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
Resolution
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
12 Bits
12 Bits
AVDD Range
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
Output
Channels
40
40
40
40
40
40
32
32
32
32
Linearity
Error (LSB)
±4
±4
±4
±4
±1
±1
±4
±4
±1
±1
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
Package Option
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
with SPI, QSPI, MICROWIRE, and DSP interface standards
and an I
2
C-compatible interface supporting a 400 kHz data
transfer rate.
An input register followed by a DAC register provides double-
buffering, allowing DAC outputs to be updated independently
or simultaneously using the LDAC input. Each channel has a
programmable gain and offset adjust register, letting the user
fully calibrate any DAC channel.
Power consumption is typically 0.25 mA per channel.
Rev. A | Page 3 of 44
AD5390/AD5391/AD5392
AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS
AV
DD
= 4.5 V to 5.5 V; DV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external.
All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
Offset Error TC
Gain Error
Gain Temperature Coefficient
2
DC Crosstalk
REFERENCE INPUT/OUTPUT
Reference Input
Reference Input Voltage
2
2
AD5390-5
AD5392-5
1
1
AD5391-5
1
Unit
12
±1
±1
4
±4
±5
± 0.024
±0.06
2
0.5
Bits
LSB max
LSB max
mV max
mV max
µV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
LSB max
Test Conditions/Comments
14
±3
−1/+2
4
±4
±5
±0.024
±0.06
2
0.5
Guaranteed monotonic over temperature.
Measured at code 32 in the linear region.
At 25°C T
MIN
to T
MAX
.
2.5
1
±1
1 V to
AV
DD
/2
2.5
1
±1
1 V to AV
DD
/2
V
MΩ min
µA max
V min/max
DC Input Impedance
Input Current
Reference Range
Reference Output
3
±1% for specified performance,
AV
DD
= 2 × REFIN + 50 mV.
Typically 100 MΩ.
Typically ±30 nA.
Output Voltage
Reference TC
Output Impedance
OUTPUT CHARACTERISTICS
Output Voltage Range
4
Short-Circuit Current
Load Current
Capacitive Load Stability
R
L
= ∞
R
L
= 5 kΩ
DC Output Impedance
MONITOR OUTPUT PIN
Output Impedance
Three-State Leakage Current
LOGIC INPUTS
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
Input Current
Pin Capacitance
2
2
2.495/2.505
1.22/1.28
±10
±15
2.2
0/AV
DD
40
±1
200
1,000
0.5
500
100
2
0.8
±10
10
2.495/2.505
1.22/1.28
±10
±15
2.2
0/AV
DD
40
±1
200
1,000
0.5
500
100
2
0.8
±10
10
V min/max
V min/max
ppm max
ppm max
kΩ typ
V min/max
mA max
mA max
pF max
pF max
Ω max
Ω typ
nA typ
Enabled via internal/external bit in control
register. REF select bit in control register
selects the reference voltage.
At ambient, optimized for 2.5 V operation.
At ambient when 1.25 V reference is selected.
Temperature range: 25°C to 85°C.
Temperature range: −40°C to +85°C.
DV
DD
= 2.7 V to 5.5 V.
V min
V max
µA max
pF max
Total for all pins. T
A
= T
MIN
to T
MAX
.
Rev. A | Page 4 of 44
AD5390/AD5391/AD5392
Parameter
LOGIC INPUTS (SCL, SDA Only)
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
I
IN
, Input Leakage Current
V
HYST
, Input Hysteresis
C
IN
, Input Capacitance
Glitch Rejection
LOGIC OUTPUTS (BUSY, SDO)
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
LOGIC OUTPUT (SDA)
V
OL
, Output Low Voltage
2
2
AD5390-5
AD5392-5
1
1
AD5391-5
1
Unit
0.7 DV
DD
0.3 DV
DD
±1
0.05 DV
DD
8
50
V min
V max
µA max
V min
pF typ
ns max
Test Conditions/Comments
SMBus-compatible at DV
DD
< 3.6 V.
SMBus-compatible at DV
DD
< 3.6 V.
0.7 DV
DD
0.3 DV
DD
±1
0.05 DV
DD
8
50
Input filtering suppresses noise spikes of
<50 ns.
DV
DD
= 5 V ± 10%, sinking 200 µA.
DV
DD
= 5 V ± 10%, SDO only, sourcing
200 µA.
DV
DD
= 2.7 V to 3.6 V, sinking 200 µA.
DV
DD
= 2.7 V to 3.6 V SDO only, sourcing
200 µA.
0.4
DV
DD
− 1
0.4
DV
DD
− 0.5
±1
5
0.4
DV
DD
− 1
0.4
DV
DD
− 0.5
±1
5
V max
V min
V max
V min
µA max
pF typ
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AV
DD
DV
DD
Power Supply Sensitivity
∆Midscale/∆AVDD
AI
DD
2
0.4
0.6
±1
8
4.5/5.5
2.7/5.5
−85
0.375
0.475
1
1
20
35
20
0.4
0.6
±1
8
4.5/5.5
2.7/5.5
−85
0.375
0.475
1
1
20
35
20
V max
V max
µA max
pF typ
V min/max
V min/max
dB typ
mA/channel
max
mA/channel
max
mA max
µA max
µA max
mW max
mW max
I
SINK
= 3 mA.
I
SINK
= 6 mA.
AI
DD
DI
DD
AI
DD
(Power-Down)
DI
DD
(Power-Down)
Power Dissipation
Outputs unloaded; boost off;
0.25 mA/channel typ.
Outputs unloaded; boost on;
0.325 mA/channel typ.
V
IH
= DV
DD
, V
IL
= DGND.
Typically 200 nA.
Typically 3 µA.
AD5390/AD5391 with outputs unloaded;
AV
DD
= DV
DD
= 5 V; boost off.
AD5392 with outputs unloaded;
AV
DD
= DV
DD
= 5 V, boost off.
AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions:
−40°C
to +85°C.
Guaranteed by characterization, not production tested.
3
Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in
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