74F648PC datasheet, PDF - EEWORLD Datasheet

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74F648PC: DescriptionF/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24, PLASTIC, DIP-24; Categorylogic logic; File Size155KB，7 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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74F648PC Overview

F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24, PLASTIC, DIP-24

74F648PC Parametric

Parameter Name	Attribute value
Maker	Texas Instruments
package instruction	DIP,
Reach Compliance Code	unknown
Other features	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
series	F/FAST
JESD-30 code	R-PDIP-T24
length	31.915 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Maximum supply current (ICC)	150 mA
propagation delay (tpd)	9 ns
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
Base Number Matches	1

74F648PC Related Products

	74F648PC	54F648DM	74F646PC
Description	F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24, PLASTIC, DIP-24	F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, CDIP24	F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24
package instruction	DIP,	DIP,	DIP,
Reach Compliance Code	unknown	unknown	unknown
Other features	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
series	F/FAST	F/FAST	F/FAST
JESD-30 code	R-PDIP-T24	R-GDIP-T24	R-PDIP-T24
Load capacitance (CL)	50 pF	50 pF	50 pF
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
Number of digits	8	8	8
Number of functions	1	1	1
Number of ports	2	2	2
Number of terminals	24	24	24
Maximum operating temperature	70 °C	125 °C	70 °C
Output characteristics	3-STATE	3-STATE	3-STATE
Output polarity	INVERTED	INVERTED	TRUE
Package body material	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE
Maximum supply current (ICC)	150 mA	150 mA	150 mA
propagation delay (tpd)	9 ns	9.5 ns	9 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.334 mm	4.572 mm	5.334 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	NO	NO	NO
technology	TTL	TTL	TTL
Temperature level	COMMERCIAL	MILITARY	COMMERCIAL
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL
width	15.24 mm	15.24 mm	15.24 mm
Maker	Texas Instruments	-	Texas Instruments
length	31.915 mm	-	31.915 mm
Base Number Matches	1	1	-

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